PSD834F4A-20UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD834F4A-20UI Datasheet PDF : 128 Pages
| |||
PSD8XXFX
MCU bus interface
15.6 80C251
The Intel 80C251 MCU features a user-configurable bus interface with four possible bus
configurations, as shown in Table 19.
The first configuration is 80C31-compatible, and the bus interface to the PSD is identical to
that shown in Figure 20. The second and third configurations have the same bus connection
as shown in Figure 21. There is only one Read Strobe (PSEN) connected to CNTL1 on the
PSD. The A16 connection to PA0 allows for a larger address input to the PSD. The fourth
configuration is shown in Figure 22. Read Strobe (RD) is connected to CNTL1 and Program
Select Enable (PSEN) is connected to CNTL2.
The 80C251 has two major operating modes: Page mode and Non-page mode. In Non-
page mode, the data is multiplexed with the lower address byte, and Address Strobe
(ALE/AS, PD0) is active in every bus cycle. In Page mode, data (D7-D0) is multiplexed with
) address (A15-A8). In a bus cycle where there is a Page hit, Address Strobe (ALE/AS, PD0)
t(s is not active and only addresses (A7-A0) are changing. The PSD supports both modes. In
c Page mode, the PSD bus timing is identical to Non-Page mode except the address hold time
u and setup time with respect to Address Strobe (ALE/AS, PD0) is not required. The PSD
d access time is measured from address (A7-A0) valid to data in valid.
Pro Figure 21. Interfacing the PSD with the 80C251, with One READ input
Obsolete Product(s) - Obsolete RESET
80C251SB
2
3
4
5
6
7
8
9
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
21 X1
20 X2
11
13
P3.0/RXD
P3.1/TXD
14
15 P3.2/INT0
16
P3.3/INT1
P3.4/T0
17
P3.5/T1
10 RST
35
EA
P0.0 43
P0.1
P0.2
42
41
P0.3 40
P0.4 39
P0.5 38
P0.6 37
P0.7 36
P2.0 24
P2.1 25
P2.2 26
P2.3 27
P2.4 28
P2.5 29
P2.6 30
P2.7 31
ALE 33
32
PSEN
18
WR
19
RD/A16
A0
A1
A2
A3
A4
A5
A6
A7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
ALE
RD
WR
A16
A0
A1
A2
A3
A4
A5
A6
A7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
PSD
30
31
32
ADIO0
ADIO1
ADIO2
33 ADIO3
34 ADIO4
35 ADIO5
36 ADIO6
37 ADIO7
39
40
ADIO8
ADIO9
41 ADIO10
42
43
ADIO11
ADIO12
44 ADIO13
45 ADIO14
46 ADIO15
47 CNTL0 (WR)
50 CNTL1(RD)
49 CNTL 2(PSEN)
10
9
8
PD0- ALE
PD1
PD2
29
PA0 28
PA1
PA2 27
PA3
PA4
PA5
25
24
23
PA6
PA7
22
21
A161
A171
7
PB0 6
PB1
PB2
PB3
PB4
5
4
3
PB5 2
PB6 52
PB7 51
PC0
PC1
20
19
PC2 18
PC3
PC4
PC5
PC6
PC7
17
14
13
12
11
RESET
RESET
48
RESET
AI02881C
1. The A16 and A17 connections are optional.
2. In non-Page-mode, AD7-AD0 connects to ADIO7-ADIO0.
Doc ID 7833 Rev 7
63/128
Share Link: 