ST72324XX-AUTO View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72324XX-AUTO

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

ST72324xx-Auto

On-chip peripherals

The SPIF bit can be cleared during a second transmission; however, it must be cleared

before the second SPIF bit in order to prevent an Overrun condition (see Overrun condition

(OVR) on page 104).

10.4.4 Clock phase and clock polarity

Four possible timing relationships may be chosen by software, using the CPOL and CPHA

bits (see Figure 52).

Note:

The idle state of SCK must correspond to the polarity selected in the SPICSR register (by

pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).

The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data

Obsolete Product(s) - Obsolete Product(s) Note:

capture clock edge

Figure 52 shows an SPI transfer with the four combinations of the CPHA and CPOL bits.

The diagram may be interpreted as a master or slave timing diagram where the SCK, MISO

and MOSI pins are directly connected between the master and the slave device.

If CPOL is changed at the communication byte boundaries, the SPI must be disabled by

resetting the SPE bit.

Figure 52. Data clock timing diagram(1)

CPHA = 1

SCK

(CPOL = 1)

SCK

(CPOL = 0)

MISO

(from master)

MOSI

(from slave)

SS

(to slave)

MSB Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSB

MSB Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1

LSB

Capture strobe

SCK

(CPOL = 1)

CPHA = 0

SCK

(CPOL = 0)

MISO

(from master)

MSB Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSB

MOSI

(from slave)

MSB

Bit 6 Bit 5 Bit 4 Bit3 Bit 2 Bit 1 LSB

SS

(to slave)

Capture strobe

1. This figure should not be used as a replacement for parametric information. Refer to the Electrical

characteristics chapter.

Doc ID 13841 Rev 1

103/193

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