ST72324XX-AUTO View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72324XX-AUTO

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

On-chip peripherals

ST72324xx-Auto

Table 56.

SPI master mode SCK frequency

Serial clock

SPR2

fCPU/4

1

fCPU/8

0

fCPU/16

0

fCPU/32

1

fCPU/64

0

fCPU/128

0

SPR1

0

0

0

1

1

1

SPR0

0

0

1

0

0

1

SPI Control/Status Register (SPICSR)

t(s) SPICSR

uc 7

rod SPIF

P RO

6

WCOL

RO

5

OVR

RO

4

MODF

RO

3

Reserved

-

Reset value: 0000 0000 (00h)

2

1

0

SOD

SSM

SSI

R/W

R/W

R/W

lete Table 57. SPICSR register description

so Bit Name

Function

Ob Serial Peripheral Data Transfer flag

roduct(s) - 7 SPIF

This bit is set by hardware when a transfer has been completed. An interrupt is

generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an

access to the SPICSR register followed by a write or a read to the SPIDR register).

0: Data transfer is in progress or the flag has been cleared

1: Data transfer between the device and an external device has been completed.

Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the

SPICSR register is read.

P Write Collision status

olete6 WCOL

This bit is set by hardware when a write to the SPIDR register is done during a

transmit sequence. It is cleared by a software sequence (see Figure 53).

0: No write collision occurred

1: A write collision has been detected.

bs SPI Overrun error

O This bit is set by hardware when the byte currently being received in the shift register

is ready to be transferred into the SPIDR register while SPIF = 1 (see Overrun

5 OVR condition (OVR) on page 104). An interrupt is generated if SPIE = 1 in SPICR

register. The OVR bit is cleared by software reading the SPICSR register.

0: No overrun error

1: Overrun error detected

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Doc ID 13841 Rev 1

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