ST72F324J2TCRE View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST72F324J2TCRE
STMicroelectronics
ST72F324J2TCRE Datasheet PDF : 194 Pages
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On-chip peripherals
ST72324xx-Auto
10.3.3 Functional description
Counter
The main block of the programmable timer is a 16-bit free running upcounter and its
associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called
high and low.
● Counter Register (CR)
– Counter High Register (CHR) is the most significant byte (MSB)
– Counter Low Register (CLR) is the least significant byte (LSB)
● Alternate Counter Register (ACR)
Obsolete Product(s) - Obsolete Product(s) Caution:
– Alternate Counter High Register (ACHR) is the most significant byte (MSB)
– Alternate Counter Low Register (ACLR) is the least significant byte (LSB)
These two read-only 16-bit registers contain the same value but with the difference that
reading the ACLR register does not clear the TOF bit (timer overflow flag), located in the
Status register (SR) (see note at the end of paragraph entitled 16-bit read sequence).
Writing in the CLR register or ACLR register resets the free running counter to the FFFCh
value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in
the 16-bit timer). The reset value of both counters is also FFFCh in one pulse mode and
PWM mode.
The timer clock depends on the clock control bits of the CR2 register, as illustrated in
Table 50. The value in the counter register repeats every 131072, 262144 or 524288 CPU
clock cycles depending on the CC[1:0] bits. The timer frequency can be fCPU/2, fCPU/4,
fCPU/8 or an external frequency.
In Flash devices, Timer A functionality has the following restrictions:
– TAOC2HR and TAOC2LR registers are write only
– Input Capture 2 is not implemented
– The corresponding interrupts cannot be used (ICF2, OCF2 forced by hardware to zero)
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Doc ID 13841 Rev 1
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