ST72F324J2TCRE View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72F324J2TCRE

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

ST72324xx-Auto

On-chip peripherals

External clock

The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register.

The status of the EXEDG bit in the CR2 register determines the type of level transition on

the external clock pin EXTCLK that will trigger the free running counter.

The counter is synchronized with the falling edge of the internal CPU clock.

A minimum of four falling edges of the CPU clock must occur between two consecutive

active edges of the external clock; thus the external clock frequency must be less than a

quarter of the CPU clock frequency.

Figure 36. Counter timing diagram, internal clock divided by 2

) CPU clock

t(s Internal reset

uc Timer clock

rod Counter register

te P Timer Overflow Flag (TOF)

FFFD FFFE FFFF 0000 0001 0002 0003

sole Figure 37. Counter timing diagram, internal clock divided by 4

Ob CPU clock

) - Internal reset

t(sTimer clock

ucCounter register FFFC FFFD

rodTimer Overflow Flag (TOF)

0000

0001

lete P Figure 38. Counter timing diagram, internal clock divided by 8

Obso CPU clock

Internal reset

Timer clock

Counter register

FFFC

FFFD

0000

Timer Overflow Flag (TOF)

Note:

The MCU is in reset state when the internal reset signal is high; when it is low the MCU is

running.

Doc ID 13841 Rev 1

79/193

Share Link: