ST72324xx-Auto
On-chip peripherals
Figure 34. Timer block diagram
fCPU
ST7 internal bus
MCU-peripheral interface
8 high
EXEDG
8 low
8-bit
buffer
88
88
88
88
16
t(s) EXTCLK
- Obsolete Produc pin
1/2
1/4
1/8
CC[1:0]
Counter
register
Alternate
Counter
register
16
Output
Compare
register
1
Output
Compare
register
2
Timer internal bus
16 16
Overflow
Detect
circuit
Output Compare
circuit
6
Input
Capture
register
1
Input
Capture
register
2
16
16
Edge Detect
circuit 1
Edge Detect
circuit 2
ICAP1
pin
ICAP2
pin
uct(s) ICF1 OCF1 TOF ICF2 OCF2TIMD 0 0
rod (Control/Status register) CSR
Latch 1
Latch 2
OCMP1
pin
OCMP2
pin
te PICIE OCIE TOIE FOLV2FOLV1OLVL2 IEDG1OLVL1 OC1E OC2E OPM PWM CC1 CC0 IEDG2EXEDG
le (Control register 1) CR1
(Control register 2) CR2
Obso (See note 1)
Timer interrupt
1. If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (see Table 25:
Interrupt mapping on page 52).
Doc ID 13841 Rev 1
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