CDB8952T-IQ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CDB8952T-IQ Datasheet PDF : 86 Pages
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CS8952T
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
Loopback, Bypass, and Receiver Error Mask Register - Address 18h (Cont.)
BIT
NAME
8
Reserved
7
Strip Preamble
TYPE
Read/Write 0
Read/Write 0
RESET
DESCRIPTION
This bit is reserved.
When set this bit causes the 7 bytes of MAC pream-
ble to be stripped off of incoming 100 Mb/s frames.
The data received across the MII will begin with the 1
byte Start of Frame Delimiter (SFD).
6
Alternate FDX CRS Read/Write 0
5
Loopback Transmit Read/Write 1
Disable
4
Code Error Report Read/Write 0
Select
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
This bit changes the behavior of the CRS pin only in
the full-duplex (FDX) mode of operation. When set,
CRS will be asserted for transmit data only. When
clear, CRS will be asserted only for receive data.
This bit controls whether loopback data is transmitted
onto the network. When set, any data transmitted
during PMD or ENDEC loopback mode will NOT be
transmitted onto the network. When clear, data will be
transmitted on the TX+/- pins as well as looped back
onto the MII pins.
When set, this bit causes code errors to be reported
by a value of 5h on RXD[3:0] and the assertion of
RX_ER.
When clear, this bit causes code errors to be reported
by a value of 6h on RXD[3:0] and the assertion of
RX_ER.
This bit is superseded by the Code Error Report
Enable bit.
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
56
DS206TPP2
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