CDB8952T-IQ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CDB8952T-IQ Datasheet PDF : 86 Pages
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CS8952T
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
Interrupt Mask Register - Address 10h
15
14
13
12
CIM Link
Unstable
Link Status Descrambler Premature
Change Lock Change End Error
11
DCR
Rollover
10
FCCR
Rollover
9
RECR
Rollover
8
Remote
Loopback
Fault
7
Reset
Complete
6
Jabber
Detect
5
Auto-Neg
Complete
4
Parallel
Detection
Fault
3
Parallel
Fail
2
Remote
Fault
1
Page
Received
0
Reserved
This register indicates which events will cause an interrupt event on the MII_IRQ pin. Each bit acts as an enable to the interrupt.
Thus, when set, the event will cause the MII_IRQ pin to be asserted. When clear, the event will not affect the MII_IRQ pin, but
the status will still be reported via the Interrupt Status Register (address 11h).
BIT
NAME
TYPE
15 CIM Link Unstable Read/Write 0
RESET
DESCRIPTION
When set, an interrupt will be generated if an unsta-
ble link condition is detected by the Carrier Integrity
Monitor function.
14 Link Status Change Read/Write 1
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated each time
the CS8952T detects a change in the link status.
13 Descrambler Lock Read/Write 0
Change
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated each time
the 100BASE-TX receive descrambler loses or
regains synchronization with the far-end.
12 Premature End
Error
Read/Write 0
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated when two
consecutive IDLES are detected in a 100BASE-TX
frame without the End-of-Stream-Delimiter sequence.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
DS206TPP2
41
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