CDB8952T-IQ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CDB8952T-IQ Datasheet PDF : 86 Pages
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CS8952T
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
Interrupt Status Register - Address 11h
15
14
13
12
CIM Link
Unstable
Link Status Descrambler Premature
Change Lock Change End Error
11
DCR
Rollover
10
FCCR
Rollover
9
RECR
Rollover
8
Remote
Loopback
Fault
7
Reset
Complete
6
Jabber
Detect
5
Auto-Neg
Complete
4
Parallel
Detection
Fault
3
Parallel
Fail
2
Remote
Fault
1
Page
Received
0
Reserved
This register indicates which event(s) caused an interrupt event on the MII_IRQ pin. All bits are self-clearing, and will thus be
cleared upon readout.
BIT
NAME
TYPE
15 CIM Link Unstable Read Only 0
RESET
14 Link Status Change Read Only 0
13 Descrambler Lock Read Only 0
Change
12 Premature End
Error
Read Only 0
11 DCR Rollover
Read Only 0
10 FCCR Rollover Read Only 0
9
RECR Rollover Read Only 0
DESCRIPTION
When set, this bit indicates that an unstable link con-
dition was detected by the Carrier Integrity Monitor
function.
When set, this bit indicates that a change has
occurred to the status of the link. The Self Status
Register (address 19h) may be read to determine the
current status of the link.
When set, this bit indicates that a change has
occurred in the status of the descrambler. The Self
Status Register (address 19h) may be read to deter-
mine the current status of the scrambler lock.
This bit is set when a premature end of frame is
detected for 100 Mb/s operation. A premature end is
defined as two consecutive IDLE patterns detected in
a frame prior to the End of Stream Delimiter.
This bit is set when the MSB of the Disconnect Count
Register (address 12h) becomes set. This should
provide ample warning to the management layer so
that the DCR may be read before rolling over.
This bit is set when the MSB of the False Carrier
Count Register (address 13h) becomes set. This
should provide ample warning to the management
layer so that the FCCR may be read before saturat-
ing.
This bit is set when the MSB of the Receive Error
Count Register (address 15h) becomes set. This
should provide ample warning to the management
layer so that the RECR may be read before rolling
over.
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
44
DS206TPP2
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