CDB8952T-IQ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CDB8952T-IQ Datasheet PDF : 86 Pages
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CS8952T
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
Interrupt Mask Register - Address 10h (Cont.)
BIT
NAME
TYPE
5
Auto-Neg Complete Read/Write 0
RESET
DESCRIPTION
When set, an interrupt will be generated once auto-
negotiation has completed successfully.
4
Parallel Detection Read/Write 0
Fault
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated if auto-nego-
tiation determines that unstable legacy link signaling
was received.
3
Parallel Fail
Read/Write 0
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated when paral-
lel detection has occurred for a technology that is not
currently advertised by the local device.
2
Remote Fault
Read/Write 0
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated if a remote
fault condition is detected either by auto-negotiation
or by the Far-End Fault Detect state machine.
1
Page Received
Read/Write 0
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt is generated each time a page
is received during auto-negotiation.
0
Reserved
Read Only 0
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
DS206TPP2
43
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