CS8952T
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
Interrupt Mask Register - Address 10h (Cont.)
BIT
NAME
11 DCR Rollover
TYPE
Read/Write 0
RESET
DESCRIPTION
When set, an interrupt will be generated if the MSB in
the DCR counter becomes set.
10 FCCR Rollover Read/Write 0
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated if the MSB in
the FCCR counter becomes set.
9
RECR Rollover Read/Write 0
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated if the MSB in
the RECR counter becomes set.
8
Remote Loopback Read/Write 0
Fault
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated if the elastic
buffer in the PMA is under-run or over-run during
Remote Loopback. This should not occur for normal
length 802.3 frames.
7
Reset Complete Read/Write 1
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated once the dig-
ital and analog sections have been reset, and a cali-
bration cycle has been performed.
6
Jabber Detect
Read/Write 0
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated when a Jab-
ber condition is detected by the 10BASE-T MAU.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
42
DS206TPP2