SMC032BF View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
SMC032BF Datasheet PDF : 91 Pages
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SMCxxxBF
8
Software interface
Software interface
8.1
CF-ATA Drive Register Set Definition and Protocol
The CompactFlash Memory Card can be configured as a high performance I/O device
through:
● Standard PC-AT disk I/O address spaces
– 1F0h-1F7h, 3F6h-3F7h (primary);
– 170h-177h, 376h-377h (secondary) with IRQ 14 (or other available IRQ).
● Any system decoded 16 Byte I/O block using any available IRQ.
● Memory space.
Communication to or from the Card is done using the Task File registers which provide all
the necessary registers for control and status information. The PCMCIA interface connects
peripherals to the host using four-register mapping methods. Table 36 is a detailed
description of these methods:
Table 36. I/O Configurations
Standards Configurations
Config Index I/O or Memory
Address
Description
0
Memory
0h-Fh, 400h-7FFh
Memory Mapped
1
I/O
xx0h-xxFh
I/O Mapped 16 Continuous Registers
2
I/O
1F0-1F7h, 3F6h-3F7h
Primary I/O Mapped
3
I/O
170-177h, 376h-377h
Secondary I/O Mapped
8.2
Memory Mapped Addressing
When the Card registers are accessed via memory references, the registers appear in the
common memory space window: 0-2KBytes as shown in Table 37 This window accesses
the Data Register FIFO. It does not allow random access to the data buffer within the Card.
Register 0 is accessed with –CE1 and –CE2 Low, as a Word register on the combined Odd
and Even Data Bus (D15 to D0). It can also be accessed with –CE1 Low and –CE2 High, by
a pair of Byte accesses to offset 0. The address space of this Word register overlaps the
address space of the Error and Feature Byte-wide registers at offset 1. When accessed
twice as Byte register with –CE1 Low, the first Byte is the even Byte of the Word and the
second is the odd Byte. A Byte access to address 0 with –CE1 High and –CE2 Low
accesses the Error (read) or Feature (write) register.
Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and
1. Register 8 is equivalent to register 0, while register 9 accesses the odd Byte. Therefore, if
the registers are Byte accessed in the order 9 then 8 the data will be transferred odd Byte
then even Byte. Repeated Byte accesses to register 8 or 0 will access consecutive (even
then odd) Bytes from the data buffer. Repeated Word accesses to register 8, 9 or 0 will
access consecutive Words from the data buffer, however repeated Byte accesses to register
9 are not supported. Repeated alternating Byte accesses to registers 8 then 9 will access
consecutive (even then odd) Bytes from the data buffer.
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