SMC032BF View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
SMC032BF Datasheet PDF : 91 Pages
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Software interface
SMCxxxBF
8.4
I/O Primary and Secondary Address Configurations
When the system decodes the Primary and Secondary Address Configurations, the
registers are accessed in the block of I/O space as shown in Table 39
As for the Memory Mapped Addressing, register 0 is accessed with –CE1 Low and –CE2
Low (and A0 don’t Care) as a Word register on the combined Odd and Even Data Bus (D15
to D0). This register may also be accessed with –CE1 Low and –CE2 High, by a pair of Byte
accesses to offset 0. The address space of this Word register overlaps the address space of
the Error and Feature Byte-wide registers at offset 1. When accessed twice as Byte register
with –CE1 Low, the first Byte is the even Byte of the Word and the second is the odd Byte. A
Byte access to register 0 with –CE1 High and –CE2 Low accesses the error (read) or
feature (write) register.
Table 39. Primary and Secondary I/O Decoding
–REG
A9 to
A4
A3 A2 A1 A0
–IORD=0
–IOWR=0
0 1F(17)h 0 0 0 0
Even Data Register
Even Data Register
0 1F(17)h 0 0 0 1
Error Register
Feature Register
0 1F(17)h 0 0 1 0
Sector Count Register
Sector Count Register
0 1F(17)h 0 0 1 1 Sector Number Register
Sector Number Register
0 1F(17)h 0 1 0 0
Cylinder Low Register
Cylinder Low Register
0 1F(17)h 0 1 0 1
Cylinder High Register
Cylinder High Register
0 1F(17)h 0 1 1 0 Select Card/Head Register Select Card/Head Register
0 1F(17)h 0 1 1 1
Status Register
Command Register
0 3F(37)h 0 1 1 0 Alternate Status Register Device Control Register
0 3F(37)h 0 1 1 1 Drive Address Register
Reserved
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