SMC032BF View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
SMC032BF Datasheet PDF : 91 Pages
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SMCxxxBF
Software interface
8.3
Contiguous I/O Mapped Addressing
When the system decodes a contiguous block of I/O registers to select the Card, the
registers are accessed in the block of I/O space decoded by the system as shown in
Table 38
As for the Memory Mapped Addressing, register 0 is accessed with –CE1 Low and –CE2
Low (and A0 don’t Care) as a Word register on the combined Odd and Even Data Bus (D15
to D0). This register may also be accessed with –CE1 Low and –CE2 High, by a pair of Byte
accesses to offset 0. The address space of this Word register overlaps the address space of
the Error and Feature Byte-wide registers at offset 1. When accessed twice as Byte register
with –CE1 Low, the first Byte is the even Byte of the Word and the second is the odd Byte. A
Byte access to register 0 with –CE1 High and –CE2 Low accesses the error (read) or
feature (write) register.
Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and
1. Register 8 is equivalent to register 0, while register 9 accesses the odd Byte. Therefore, if
the registers are Byte accessed in the order 9 then 8 the data will be transferred odd Byte
then even Byte. Repeated Byte accesses to register 8 or 0 will access consecutive (even
than odd) Bytes from the data buffer. Repeated Word accesses to register 8, 9 or 0 will
access consecutive Words from the data buffer, however repeated Byte accesses to register
9 are not supported. Repeated alternating Byte accesses to registers 8 then 9 will access
consecutive (even then odd) Bytes from the data buffer.
Table 38. Contiguous I/O Decoding
–REG
A10 to
A4
A3
A2
A1
A0 Offset
–IORD=0
–IOWR=0
0
X
0 0 0 0 0h
Even Data Register
Even Data Register
0
X
0 0 0 1 1h
Error Register
Feature Register
0
X
0 0 1 0 2h Sector Count Register Sector Count Register
0
X
0 0 1 1 3h
Sector Number
Register
Sector Number
Register
0
X
0 1 0 0 4h Cylinder Low Register Cylinder Low Register
0
X
0 1 0 1 5h Cylinder High Register Cylinder High Register
0
X
0 1 1 0 6h
Select Card/Head
Register
Select Card/Head
Register
0
X
0 1 1 1 7h
Status Register
Command Register
0
X
1 0 0 0 8h
Dup. Even Data
Register
Dup. Even Data
Register
0
X
1 0 0 1 9h Dup. Odd Data Register Dup. Odd Data Register
0
X
1 1 0 1 Dh
Dup. Error Register Dup. Feature Register
0
X
1 1 1 0 Eh
Alternate Status
Register
Device Control Register
0
X
1 1 1 1 Fh Drive Address Register
Reserved
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