T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
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T2080NXE8MQLB Datasheet PDF : 186 Pages
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Electrical characteristics
Table 46. eSDHC interface DC electrical characteristics (dual-voltage cards)3 (continued)
Characteristic
Symbol
Condition
Min
Max
Unit Notes
Output high voltage
VOH
IOH = -100 μA
VDD - 0.2
-
V
2
Output low voltage
VOL
IOL = 2 mA
-
0.3
V
2
1. The min VIL and VIH values are based on the respective min and max VIN values found in Table 3.
2. Open-drain mode is for MMC cards only.
3. For recommended operating conditions, see Table 3.
4. SDHC interface is powered by OVDD and CVDD. The VDD and VIN in the table above should be replaced by the respective
I/O power supply.
3.14.2 eSDHC AC timing specifications
This table provides the eSDHC AC timing specifications as defined in Figure 22 and
Figure 23 (OVDD/CVDD = 1.8 V or 3.3 V).
Table 47. eSDHC AC timing specifications (High Speed/Full Speed)6
Parameter
Symbol1 Min
Max
Unit
Notes
SDHC_CLK clock frequency
SD/SDIO (full-speed/high-speed fSCK
0
mode)
25/50 MHz
2, 4
MMC full-speed/high-speed mode
20/52
SDHC_CLK clock low time (full-speed/high-speed mode)
tSCKL
10/7
—
ns
4
SDHC_CLK clock high time (full-speed/high-speed mode)
tSCKH
10/7
—
ns
4
SDHC_CLK clock rise and fall times
tSCKR/
—
3
ns
4
tSCKF
Input setup times: SDHC_CMD, SDHC_DATx to SDHC_CLK
tNIIVKH
2.5
—
ns
3, 4, 5
Input hold times: SDHC_CMD, SDHC_DATx to SDHC_CLK
tNIIXKH
2.5
—
ns
4, 5
Output hold time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid tNIKHOX -3
—
ns
4, 5
Output delay time: SDHC_CLK to SDHC_CMD, SDHC_DATx valid tNIKHOV —
3
ns
4, 5
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state)
for inputs and (first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFHSKHOV symbolizes eSDHC
high-speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the output (O) reaching
the invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing
the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F
(fall).
2. In full-speed mode, the clock frequency value can be 0-25 MHz for an SD/SDIO card and 0-20 MHz for an MMC card. In
high-speed mode, the clock frequency value can be 0-50 MHz for an SD/SDIO card and 0-52 MHz for an MMC card.
3. To satisfy setup timing, one-way board-routing delay between Host and Card, on SDHC_CLK, SDHC_CMD, and
SDHC_DATx should not exceed 1 ns for any high speed MMC card. For any high speed or default speed mode SD card, the
one way board routing delay between Host and Card, on SDHC_CLK, SDHC_CMD, and SDHC_DATx should not exceed
1.5ns.
4. CCARD ≤ 10 pF, (1 card), and CL = CBUS + CHOST + CCARD ≤ 40 pF.
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
86
NXP Semiconductors
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