Electrical characteristics
Table 48. eSDHC AC timing (eMMC HS200)
Parameter
SDHC_CLK clock frequency
eMMC HS200 mode
SDHC_CLK duty cycle
SDHC_CLK clock rise and fall times
Output hold time: SDHC_CLK to
SDHC_CMD, SDHC DATx valid,
SDHC_CMD_DIR,
SDHC_DATx_DIR
eMMC HS200 mode
Output delay time: SDHC_CLK to eMMC HS200 mode
SDHC_CMD, SDHC DATx valid,
SDHC_CMD_DIR,
SDHC_DATx_DIR
Input data window (UI)
eMMC HS200 mode
Symbol Min
fSCK
—
—
47
tSCKR/
—
tSCKF
tNIKHOX 1.6
Max
175
53
1
—
tNIKHOV
—
3.9
tIDV
0.475
—
Notes:
1. CL = CBUS + CHOST + CCARD ≤ 10 pF.
2. For recommended operating conditions, see Table 3.
Units
MHz
%
ns
Notes
—
—
1
ns
—
ns
—
Unit
—
interval
This figure provides the HS200 mode timing diagram.
Tclk
SDHC_CLK
SDHC_CMD/
SDHC_DAT input
T IDV
DATA
SDHC_CMD/SDHC_CMD_DIR
SDHC_DAT/SDHC_DATn_DIR
output
DATA
TNIKHOV
DATA
TNIKHOX
Figure 24. eMMC HS200 mode timing diagram
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
88
NXP Semiconductors