T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

T2080NXE8MQLB

T2080 QorIQ integrated multicore communications processor

NXP Semiconductors. 

Electrical characteristics

Table 52. JTAG AC timing specifications4 (continued)

Parameter

Symbol1

Min

Max

Unit Notes

Output hold times

Notes:

tJTKLDX

0

—

ns

3

1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs

and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT)

with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the

high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D)

reaching the invalid state (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that in general, the clock

reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall

times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2.TRST_B is an asynchronous level sensitive signal. The setup time is for test purposes only.

3. All outputs are measured from the midpoint voltage of the falling edge of tTCLK to the midpoint of the signal in question. The

output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays must be

added for trace lengths, vias, and connectors in the system.

4. For recommended operating conditions, see Table 3.

5. LP_TMP_DETECT pin requires 9.5ns input setup time for the board JTAG test to go through runTESTIdle.

This figure provides the AC test load for TDO and the boundary-scan outputs of the

device.

Output

Z0= 50 Ω

RL = 50 Ω

OVDD/2

Figure 25. AC test load for the JTAG interface

This figure provides the JTAG clock input timing diagram.

JTAG external clock

VM

VM

VM

tJTKHKL

tJTGR

tJTG

VM = Midpoint voltage (OVDD/2)

Figure 26. JTAG clock input timing diagram

tJTGF

QorIQ T2080 Data Sheet, Rev. 3, 03/2018

NXP Semiconductors

91

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