T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
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Description
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T2080NXE8MQLB Datasheet PDF : 186 Pages
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Electrical characteristics
Table 55. I2C AC timing specifications5
Parameter
Symbol1
Min
Max
Unit Notes
SCL clock frequency
fI2C
0
Low period of the SCL clock
tI2CL
1.3
High period of the SCL clock
tI2CH
0.6
Setup time for a repeated START condition
tI2SVKH
0.6
Hold time (repeated) START condition (after this period, the first tI2SXKL
0.6
clock pulse is generated)
400
kHz 2
-
μs
-
-
μs
-
-
μs
-
-
μs
-
Data setup time
Data input hold time:
tI2DVKH
100
-
tI2DXKL
CBUS compatible masters
-
-
ns
-
μs
3
I2C bus devices
0
-
Data output delay time
Setup time for STOP condition
Bus free time between a STOP and START condition
Noise margin at the LOW level for each connected device
(including hysteresis)
tI2OVKL
tI2PVKH
tI2KHDX
VNL
-
0.9
0.6
-
1.3
-
0.1 x OVDD -
μs
4
μs
-
μs
-
V
-
Noise margin at the HIGH level for each connected device
VNH
0.2 x OVDD -
(including hysteresis)
V
-
Capacitive load for each bus line
Cb
-
400
pF
-
Notes:
1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with
respect to the time data input signals (D) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high
(H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the START condition
(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C
timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative to the tI2C clock
reference (K) going to the high (H) state or setup time.
2. The requirements for I2C frequency calculation must be followed. See Determining the I2C Frequency Divider Ratio for
SCL (AN2919).
3. As a transmitter, the chip provides a delay time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL
signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP
condition. When the chip acts as the I2C bus master while transmitting, it drives both SCL and SDA. As long as the load on
SCL and SDA are balanced, the chip does not generate an unintended START or STOP condition. Therefore, the 300 ns
SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for the
chip as transmitter, see Determining the I2C Frequency Divider Ratio for SCL (AN2919).
4. The maximum tI2OVKL has to be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal.
5. For recommended operating conditions, see Table 3.
This figure provides the AC test load for the I2C.
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
94
NXP Semiconductors
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