T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
T2080NXE8MQLB Datasheet PDF : 186 Pages
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Electrical characteristics
SDn_REF_CLKn_P
SDn_REF_CLKn_N
50 Ω
50 Ω
Input
amp
Figure 33. Receiver of SerDes reference clocks
The characteristics of the clock signals are as follows:
• The SerDes transceivers core power supply voltage requirements (SVDDn) are as
specified in Recommended operating conditions.
• The SerDes reference clock receiver reference circuit structure is as follows:
• The SDn_REF_CLKn_P and SDn_REF_CLKn_N are internally AC-coupled
differential inputs as shown in Figure 33. Each differential clock input
(SDn_REF_CLKn_P or SDn_REF_CLKn_N) has on-chip 50-Ω termination to
SGNDnfollowed by on-chip AC-coupling.
• The external reference clock driver must be able to drive this termination.
• The SerDes reference clock input can be either differential or single-ended. See
the differential mode and single-ended mode descriptions below for detailed
requirements.
• The maximum average current requirement also determines the common mode
voltage range.
• When the SerDes reference clock differential inputs are DC coupled externally
with the clock driver chip, the maximum average current allowed for each input
pin is 8 mA. In this case, the exact common mode input voltage is not critical as
long as it is within the range allowed by the maximum average current of 8 mA
because the input is AC-coupled on-chip.
• This current limitation sets the maximum common mode input voltage to be less
than 0.4 V (0.4 V ÷ 50 = 8 mA) while the minimum common mode input level is
0.1 V above SGNDn. For example, a clock with a 50/50 duty cycle can be
produced by a clock driver with output driven by its current source from 0 mA to
16 mA (0-0.8 V), such that each phase of the differential input has a single-
ended swing from 0 V to 800 mV with the common mode voltage at 400 mV.
• If the device driving the SDn_REF_CLKn_P and SDn_REF_CLKn_N inputs
cannot drive 50 Ω to SGNDn DC or the drive strength of the clock driver chip
exceeds the maximum input current limitations, it must be AC-coupled off-chip.
• The input amplitude requirement is described in detail in the following sections.
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors
101
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