T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

T2080NXE8MQLB

T2080 QorIQ integrated multicore communications processor

NXP Semiconductors. 

Electrical characteristics

Table 60. SDn_REF_CLKn_P/ SDn_REF_CLKn_N input clock requirements (SVDDn = 1.0 V)1

Parameter

Symbol

Min

Typ

Max Unit Notes

10. Measurement taken from single-ended waveform

11. Matching applies to rising edge for SDn_REF_CLKn_P and falling edge rate for SDn_REF_CLKn_N. It is measured using

a 200 mV window centered on the median cross point where SDn_REF_CLKn_P rising meets SDn_REF_CLKn_N falling.

The median cross point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations.

The rise edge rate of SDn_REF_CLKn_P must be compared to the fall edge rate of SDn_REF_CLKn_N, the maximum

allowed difference should not exceed 20% of the slowest edge rate. See Figure 38.

This table lists the AC requirements for SerDes reference clocks for protocols running at

data rates greater than 8 GBaud.

This includes XFI (10.3125 GBaud) and 10GBase-KR (10.3125 GBaud), SerDes

reference clocks to be guaranteed by the customer's application design.

Table 61. SDn_REF_CLKn_P/ SDn_REF_CLKn_N input clock requirements (SVDDn = 1.0 V)1

Parameter

Symbol Min

Typ

Max Unit Notes

SDn_REF_CLKn_P/ SDn_REF_CLKn_N frequency range

SDn_REF_CLKn_P/ SDn_REF_CLKn_N clock frequency

tolerance

tCLK_REF

tCLK_TOL

-

-100

156.25

-

-

MHz 2

100 ppm -

SDn_REF_CLKn_P/ SDn_REF_CLKn_N reference clock

tCLK_DUTY 40

50

duty cycle

60

%

3

SDn_REF_CLKn_P/ SDn_REF_CLKn_N single side band @1 kHz -

-

noise

SDn_REF_CLKn_P/ SDn_REF_CLKn_N single side band @10 kHz -

-

noise

-85

dBC/Hz 4

-108 dBC/Hz 4

SDn_REF_CLKn_P/ SDn_REF_CLKn_N single side band @100 -

-

noise

kHz

SDn_REF_CLKn_P/ SDn_REF_CLKn_N single side band @1 MHz -

-

noise

-128 dBC/Hz 4

-138 dBC/Hz 4

SDn_REF_CLKn-P/ SDn_REF_CLKn_N single side band @10MHz -

-

noise

SDn_REF_CLKn_P/ SDn_REF_CLKn_N random jitter (1.2 tCLK_RJ -

-

MHz to 15 MHz)

-138 dBC/Hz 4

0.8

ps

-

SDn_REF_CLKn_P/ SDn_REF_CLKn_N total reference

tCLK_TJ

-

-

clock jitter at 10-12 BER (1.2 MHz to 15 MHz)

11

ps

-

SDn_REF_CLKn_P/ SDn_REF_CLKn_N spurious noise (1.2 -

MHz to 15 MHz)

Notes:

-

-

-75

dBC -

1. For recommended operating conditions, see Table 3.

2. Caution: Only 156.25 have been tested. In-between values do not work correctly with the rest of the system.

3. Measurement taken from differential waveform.

4. Per XFP Spec. Rev 4.5, the Module Jitter Generation spec at XFI Optical Output is 10mUI (RMS) and 100 mUI (p-p). In the

CDR mode the host is contributing 7 mUI (RMS) and 50 mUI (p-p) jitter.

QorIQ T2080 Data Sheet, Rev. 3, 03/2018

NXP Semiconductors

105

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