T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
T2080NXE8MQLB Datasheet PDF : 186 Pages
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Electrical characteristics
This includes PCI Express (2.5, 5 and 8 GT/s), SGMII (1.25GBaud), 2.5x SGMII (3.125
GBaud), Serial RapidIO (2.5, 3.125 and 5 GBaud), Aurora (2.5 and 5 GBaud), HiGig/
HiGig2 (3.125 GBaud), HiGig/HiGig2 (3.75 GBaud), XAUI (3.125 GBaud), SATA (1.5
and 3 Gbps), 1000Base-KX (3.125 GBaud) and SerDes reference clocks to be guaranteed
by the customer's application design.
Table 60. SDn_REF_CLKn_P/ SDn_REF_CLKn_N input clock requirements (SVDDn = 1.0 V)1
Parameter
Symbol
Min
Typ
Max Unit Notes
SDn_REF_CLKn_P/ SDn_REF_CLKn_N frequency tCLK_REF
-
100/125/156.25 -
MHz 2
range
SDn_REF_CLKn_P/ SDn_REF_CLKn_N clock
frequency tolerance
tCLK_TOL
-300 -
300 ppm 3
SDn_REF_CLKn_P/ SDn_REF_CLKn_N clock
frequency tolerance
tCLK_TOL
-100 -
100 ppm 4
SDn_REF_CLKn_P/ SDn_REF_CLKn_N reference tCLK_DUTY
clock duty cycle
40
50
60
%
5
SDn_REF_CLKn_P/ SDn_REF_CLKn_N max
deterministic peak-to-peak jitter at 10-6 BER
tCLK_DJ
-
-
42
ps
-
SDn_REF_CLKn_P/ SDn_REF_CLKn_N total
tCLK_TJ
reference clock jitter at 10-6 BER (peak-to-peak jitter
at refClk input)
-
-
86
ps
6
SDn_REF_CLKn_P/ SDn_REF_CLKn_N 10 kHz to tREFCLK-LF-RMS -
-
1.5 MHz RMS jitter
3
ps
7
RMS
SDn_REF_CLKn_P/ SDn_REF_CLKn_N > 1.5 MHz tREFCLK-HF-RMS -
-
to Nyquist RMS jitter
3.1
ps
7
RMS
SDn_REF_CLKn_P/ SDn_REF_CLKn_N RMS
tREFCLK-RMS-DC -
-
reference clock jitter
1
ps
8
RMS
SDn_REF_CLKn_P/ SDn_REF_CLKn_N rising/
tCLKRR/tCLKFR 1
-
falling edge rate
4
V/ns 9
Differential input high voltage
Differential input low voltage
Rising edge rate (SDn_REF_CLKn_P) to falling
edge rate (SDn_REF_CLKn_P) matching
VIH
VIL
Rise-Fall
Matching
200 -
-
-
-
-
-
mV
-200 mV
20
%
5
5
10, 11
Notes:
1. For recommended operating conditions, see Table 3.
2. Caution: Only 100, 125 and 156.25 have been tested.In-between values do not work correctly with the rest of the system.
3. For PCI Express (2.5, 5, 8 GT/s)
4. For SGMII, 2.5x SGMII, QSGMII, sRIO, HiGig/HiGig2, XAUI
5. Measurement taken from differential waveform
6. Limits from PCI Express CEM Rev 2.0
7. For PCI Express-5 GT/s, per PCI Express base specification rev 3.0
8. For PCI-Express-8 GT/s, per PCI-Express base specification rev 3.0
9. Measured from -200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLKn_P minus
SDn_REF_CLKn_N). The signal must be monotonic through the measurement region for rise and fall time. The 400 mV
measurement window is centered on the differential zero crossing. See Figure 37.
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
104
NXP Semiconductors
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