T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

T2080NXE8MQLB

T2080 QorIQ integrated multicore communications processor

NXP Semiconductors. 

Electrical characteristics

The DC and AC specification of SerDes data lanes are defined in each interface protocol

section below based on the application usage:

• PCI Express

• Serial RapidIO (sRIO)

• XAUI interface

• Aurora interface

• Serial ATA (SATA) interface

• SGMII interface

• HiGig/HiGig2 interface

• XFI interface

• 10GBase-KR interface

• 1000Base-KX interface

Note that external AC-coupling capacitor is required for the above serial transmission

protocols with the capacitor value defined in the specification of each protocol section.

3.19.4 PCI Express

This section describes the clocking dependencies, DC and AC electrical specifications for

the PCI Express bus.

3.19.4.1 Clocking dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 parts per

million (ppm) of each other at all times. This is specified to allow bit rate clock sources

with a ±300 ppm tolerance.

3.19.4.2 PCI Express clocking requirements for SDn_REF_CLKn_P and

SDn_REF_CLKn_N

SerDes 1-2 (SD[1:2]_REF_CLK[1:2]_P and SD[1:2]_REF_CLK[1:2]_N) may be used

for various SerDes PCI Express configurations based on the RCW Configuration field

SRDS_PRTCL. PCI Express is not supported on SerDes 1 and 2.

NOTE

PCI Express operating in x8 mode is only supported at 2.5 and

5.0 GT/s.

For more information on these specifications, see SerDes reference clocks.

QorIQ T2080 Data Sheet, Rev. 3, 03/2018

NXP Semiconductors

107

Share Link: