T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
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T2080NXE8MQLB Datasheet PDF : 186 Pages
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Electrical characteristics
3.19.2.3 DC-level requirement for SerDes reference clocks
The DC level requirement for the SerDes reference clock inputs is different depending on
the signaling mode used to connect the clock driver chip and SerDes reference clock
inputs, as described below.
Differential mode:
• The input amplitude of the differential clock must be between 400 mV and 1600 mV
differential peak-to-peak (or between 200 mV and 800 mV differential peak). In
other words, each signal wire of the differential pair must have a single-ended swing
of less than 800 mV and greater than 200 mV. This requirement is the same for both
external DC-coupled or AC-coupled connection.
• For an external DC-coupled connection, as described in SerDes reference clock
receiver characteristics, the maximum average current requirements sets the
requirement for average voltage (common mode voltage) as between 100 mV and
400 mV. Figure 34 shows the SerDes reference clock input requirement for DC-
coupled connection scheme.
SDn_REF_CLKn_P
200 mV < Input amplitude or differential peak < 800 mV
Vmax < 800mV
100 mV < Vcm < 400 mV
SDn_REF_CLKn_N
Vmin > 0 V
Figure 34. Differential reference clock input DC requirements (external DC-coupled)
• For an external AC-coupled connection, there is no common mode voltage
requirement for the clock driver. Because the external AC-coupling capacitor blocks
the DC level, the clock driver and the SerDes reference clock receiver operate in
different common mode voltages. The SerDes reference clock receiver in this
connection scheme has its common mode voltage set to SGNDn. Each signal wire of
the differential inputs is allowed to swing below and above the common mode
voltage (SGNDn). Figure 35 shows the SerDes reference clock input requirement for
AC-coupled connection scheme.
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
102
NXP Semiconductors
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