T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
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T2080NXE8MQLB Datasheet PDF : 186 Pages
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Electrical characteristics
3.19.4.4 PCI Express DC physical layer receiver specifications
This section discusses the PCI Express DC physical layer receiver specifications for 2.5
GT/s, 5 GT/s and 8 GT/s.
This table defines the DC specifications for the PCI Express 2.0 (2.5 GT/s) differential
input at all receivers. The parameters are specified at the component pins.
Table 65. PCI Express 2.0 (2.5 GT/s) differential receiver input DC specifications (SVDD = 1.0
V)4
Parameter
Symbol
Min Typ Max Units
Notes
Differential input peak-to-peak
voltage
VRX-DIFFp-p
120 1000 1200 mV
VRX-DIFFp-p = 2 x |VRX-D+ - VRX-D-| See
Note 1.
DC differential input impedance
ZRX-DIFF-DC
80 100 120 Ω
Receiver DC differential mode
impedance. See Note 2
DC input impedance
ZRX-DC
40 50
60 Ω
Required receiver D+ as well as D- DC
Impedance (50 ± 20% tolerance). See
Notes 1 and 2.
Powered down DC input impedance ZRX-HIGH-IMP-DC 50 -
-
kΩ Required receiver D+ as well as D- DC
Impedance when the receiver
terminations do not have power. See
Note 3.
Electrical idle detect threshold
VRX-IDLE-DET-
DIFFp-p
65 -
175 mV
VRX-IDLE-DET-DIFFp-p = 2 x |VRX-D+ -VRX-
D-|
Measured at the package pins of the
receiver
Notes:
1. Measured at the package pins with a test load of 50Ω to GND on each pin.
2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This
helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must
be measured at 300 mV above the receiver ground.
4. For recommended operating conditions, see Table 3.
This table defines the DC specifications for the PCI Express 2.0 (5 GT/s) differential
input at all receivers. The parameters are specified at the component pins.
Table 66.
PCI
V)4
Express
2.0
(5
GT/s)
differential
receiver
input
DC
specifications
(SVDD
=
1.0
Parameter
Symbol
Differential input peak-to-peak voltage VRX-DIFFp-p
DC differential input impedance
ZRX-DIFF-DC
Min Typ
120 1000
80 100
Max Units
Notes
1200 mV
VRX-DIFFp-p = 2 x |VRX-D+ - VRX-D-|
See Note 1.
120 Ω
Receiver DC differential mode
impedance. See Note 2
Table continues on the next page...
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
110
NXP Semiconductors
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