T2080NXE8MQLB View Datasheet(PDF) - NXP Semiconductors.
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T2080NXE8MQLB Datasheet PDF : 186 Pages
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Electrical characteristics
within a differential pair. There is only one signal trace curve in a differential
waveform. The voltage represented in the differential waveform is not referenced to
ground. See Figure 37 as an example for differential waveform.
Common Mode Voltage, Vcm
The common mode voltage is equal to half of the sum of the voltages between each
conductor of a balanced interchange circuit and ground. In this example, for SerDes
output, Vcm_out = (VSD_TXn_P+ VSD_TXn_N) ÷ 2 = (A + B) ÷ 2, which is the arithmetic
mean of the two complimentary output voltages within a differential pair. In a system,
the common mode voltage may often differ from one component's output to the other's
input. It may be different between the receiver input and driver output circuits within
the same component. It is also referred to as the DC offset on some occasions.
To illustrate these definitions using real values, consider the example of a current mode
logic (CML) transmitter that has a common mode voltage of 2.25 V and outputs, TD and
TD_B. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak voltage swing
of each signal (TD or TD_B) is 500 mV p-p, which is referred to as the single-ended
swing for each signal. Because the differential signaling environment is fully symmetrical
in this example, the transmitter output's differential swing (VOD) has the same amplitude
as each signal's single-ended swing. The differential output signal ranges between 500
mV and -500 mV. In other words, VOD is 500 mV in one phase and -500 mV in the other
phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential
voltage (VDIFFp-p) is 1000 mV p-p.
3.19.2 SerDes reference clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates
the clock used by the corresponding SerDes lanes. The SerDes reference clocks inputs are
SD1_REF_CLK[1:2]_P and SD1_REF_CLK[1:2]_N for SerDes 1,
SD2_REF_CLK[1:2]_P and SD2_REF_CLK[1:2]_N for SerDes 2.
SerDes 1-2 may be used for various combinations of the following IP blocks based on the
RCW Configuration field SRDS_PRTCLn:
• SerDes 1: SGMII (1.25 and 3.125 GBaud), PEX3 (2.5, 5 and 8 GT/s), PEX4 (2.5 and
5 GT/s), HiGig/HiGig2 (3.125GBaud), HiGig/HiGig2 (3.75GBaud) or XAUI
(3.125GBaud)XFI (10.3125 GBaud only), 1000Base-KX (3.125GBaud), 10GBase-
KR (10.3125 GBaud only)
• SerDes 2: PEX1 (2.5, 5 and 8 GT/s), PEX2 (2.5 and 5 GT/s), Aurora (2.5 and 5
GBaud), SATA1/2 (1.5 and 3.0 Gbps) and SRIO1/2 (2.5, 3.125 and 5 GBaud)
The following sections describe the SerDes reference clock requirements and provide
application information.
QorIQ T2080 Data Sheet, Rev. 3, 03/2018
NXP Semiconductors
99
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