ST72325J4B5 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST72325J4B5
STMicroelectronics
ST72325J4B5 Datasheet PDF : 193 Pages
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ST72325
12.11 COMMUNICATION INTERFACE CHARACTERISTICS
12.11.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for VDD,
fCPU, and TA unless otherwise specified.
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Symbol
Parameter
Conditions
Min
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
tr(SCK)
tf(SCK)
tsu(SS)
th(SS)
tw(SCKH)
tw(SCKL)
tsu(MI)
tsu(SI)
th(MI)
th(SI)
ta(SO)
tdis(SO)
tv(SO)
th(SO)
tv(MO)
th(MO)
SPI clock rise and fall time
SS setup time
SS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Master
Slave
fCPU/128 fCPU/4
fCPU=8MHz 0.0625
2
MHz
fCPU=8MHz
0
fCPU/2
4
see I/O port pin description
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
Slave (after enable edge)
Master (before capture edge)
120
120
100
90
100
100
100
ns
100
0
120
240
90
0
0.25
0.25
tCPU
Figure 90. SPI Slave Timing Diagram with CPHA=0 3)
SS INPUT
CPHA=0
CPOL=0
CPHA=0
CPOL=1
tsu(SS)
ta(SO)
MISO OUTPUT
see note 2
tsu(SI)
tc(SCK)
ttww((SSCCKKLH))
tv(SO)
MSB OUT
th(SI)
BIT6 OUT
th(SS)
th(SO)
tr(SCK)
tf(SCK)
LSB OUT
tdis(SO)
see
note 2
MOSI INPUT
MSB IN
BIT1 IN
LSB IN
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
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