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ST72325J4B5 View Datasheet(PDF) - STMicroelectronics

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Description
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ST72325J4B5 Datasheet PDF : 193 Pages
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ST72325
ADC CHARACTERISTICS (Cont’d)
Figure 94. RAIN max. vs fADC with CAIN=0pF1)
45
40
35
2 MHz
30
1 MHz
25
20
15
10
5
0
0
10
30
70
CPARASITIC (pF)
Figure 96. Typical A/D Converter Application
VAIN
RAIN
AINx
CAIN
Figure
95.
Recommended
CAIN
&
RAIN
2)
values.
1000
Cain 10 nF
100
Cain 22 nF
Cain 47 nF
10
1
0.1
0.01
0.1
1
10
fAIN(KHz)
VDD
VT
0.6V
VT
0.6V
ST72XXX
2kΩ(max)
10-Bit A/D
Conversion
IL
±1µA
CADC
12pF
Notes:
1. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-
pacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
2. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and
decreased to allow the use of a larger serial resistor (RAIN).
170/193

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