ST72361J4-AUTO View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72361J4-AUTO

8-bit MCU for automotive with Flash or ROM, 10-bit ADC, 5 timers, SPI, LINSCI™

STMicroelectronics 

ST72361xx-Auto

Electrical characteristics

19.9 I/O port pin characteristics

19.9.1 General characteristics

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Table 105. I/O characteristics

Symbol

Parameter

Conditions

Min

Typ Max Unit

VIL Input low level voltage(1)

VIH Input high level voltage(1)

CMOS ports

Vhys Schmitt trigger voltage hysteresis(2)

VIL Input low level voltage(1)

VIH Input high level voltage(1)

TTL ports

Vhys Schmitt trigger voltage hysteresis(2)

0.3 x VDD

0.7 x VDD

1

V

0.8

2

400

mV

Injected Current on PB3

IINJ(PIN)

Flash devices

0

ROM devices

Injected Current on any other I/O pin VDD = 5V

+4

±4

±4

mA

IINJ(PIN) Total injected current (sum of all I/O

(3)

and control pins)(4)

±25

Input leakage current on robust pins See Section 20.13: 10-bit ADC characteristics

Ilkg

Input leakage current(5)

IS

Static current consumption(6)

VSS  VIN  VDD

Floating input mode

±1

µA

200

RPU Weak pull-up equivalent resistor(7) VIN  VSS VDD = 5V

50

90

250

k

CIO I/O pin capacitance

5

pF

tf(IO)out

tr(IO)out

tw(IT)in

Output high to low level fall time

Output low to high level rise time

External interrupt pulse time(4)

CL = 50pF

Between 10% and 90%

25

1

ns

tCPU

1. Data based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

3. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to IINJ(PIN)

specification. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. Refer to

Section 20.2: Absolute maximum ratings for more details.

4. To generate an external interrupt, a minimum pulse width must be applied on an I/O port pin configured as an external

interrupt source.

5. Leakage could be higher than max. if negative current is injected on adjacent pins.

6. Configuration not recommended, all unused pins must be kept at a fixed voltage: Using the output mode of the I/O, for

example, or an external pull-up or pull-down resistor (see Figure 126). Data based on design simulation and/or technology

characteristics, not tested in production.

7. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described in

Figure 127).

Doc ID 12468 Rev 3

241/279

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