ADSP-BF526BBCZ-4AX View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-BF526BBCZ-4AX

Blackfin® Embedded Processor

Analog Devices 

ADSP-BF522/523/524/525/526/527

Preliminary Technical Data

10/100 Ethernet MAC Controller Timing

Table 50 through Table 55 and Figure 35 through Figure 40

describe the 10/100 Ethernet MAC Controller operations.

Table 50. 10/100 Ethernet MAC Controller Timing: MII Receive Signal

Parameter1

tERXCLKF

ERxCLK Frequency (fSCLK = SCLK Frequency)

tERXCLKW

ERxCLK Width (tERxCLK = ERxCLK Period)

tERXCLKIS

Rx Input Valid to ERxCLK Rising Edge (Data In Setup)

tERXCLKIH

ERxCLK Rising Edge to Rx Input Invalid (Data In Hold)

1 MII inputs synchronous to ERxCLK are ERxD3–0, ERxDV, and ERxER.

VDDEXT = 1.8 V

Min

Max

None

tERxCLK x 40%

7.5

25 + 1%

fSCLK + 1%

tERxCLK x 60%

7.5

VDDEXT = 2.5/3.3 V

Min

Max

Unit

None

tERxCLK x 35%

7.5

25 + 1% MHz

fSCLK + 1%

tERxCLK x 65% ns

ns

7.5

ns

Table 51. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal

Parameter1

VDDEXT = 1.8 V

Min

Max

tETXCLKF

tETXCLKW

tETXCLKOV

tETXCLKOH

ETxCLK Frequency (fSCLK = SCLK Frequency)

None

ETxCLK Width (tETxCLK = ETxCLK Period)

tETxCLK x 40%

ETxCLK Rising Edge to Tx Output Valid (Data Out Valid)

ETxCLK Rising Edge to Tx Output Invalid (Data Out

0

Hold)

25 + 1%

fSCLK + 1%

tETxCLK x 60%

20

1 MII outputs synchronous to ETxCLK are ETxD3–0.

VDDEXT = 2.5/3.3 V

Min

Max

Unit

None

tETxCLK x 35%

25 + 1% MHz

fSCLK + 1%

tETxCLK x 65% ns

20

ns

0

ns

Table 52. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal

Parameter1

tEREFCLKF

REF_CLK Frequency (fSCLK = SCLK Frequency)

tEREFCLKW

tEREFCLKIS

EREF_CLK Width (tEREFCLK = EREFCLK Period)

Rx Input Valid to RMII REF_CLK Rising Edge (Data In

Setup)

tEREFCLKIH

RMII REF_CLK Rising Edge to Rx Input Invalid (Data In

Hold)

1 RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER.

VDDEXT = 1.8 V

Min

Max

VDDEXT = 2.5/3.3 V

Min

Max

Unit

None

50 + 1%

None

50 + 1% MHz

2 x fSCLK + 1%

2 x fSCLK + 1%

tEREFCLK x 40% tEREFCLK x 60% tEREFCLK x 35% tEREFCLK x 65% ns

4

4

ns

2

2

ns

Table 53. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal

Parameter1

tEREFCLKOV

RMII REF_CLK Rising Edge

to Tx Output Valid (Data Out Valid)

tEREFCLKOH

RMII REF_CLK Rising Edge

to Tx Output Invalid (Data Out Hold)

1 RMII outputs synchronous to RMII REF_CLK are ETxD1–0.

ADSP-BF522/524/526

VDDEXT =

1.8 V

VDDEXT =

2.5/3.3 V

Min Max Min Max

8.1

8.1

ADSP-BF523/525/527

VDDEXT =

1.8 V

VDDEXT =

2.5/3.3 V

Min Max Min Max Unit

7.5

7.5 ns

2

2

2

2

ns

Rev. PrG | Page 60 of 80 | February 2009

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