ADSP-BF526BBCZ-4AX View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-BF526BBCZ-4AX Datasheet PDF : 80 Pages
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Preliminary Technical Data
ADSP-BF522/523/524/525/526/527
Table 54. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal
Parameter1, 2
VDDEXT = 1.8 V
Min
Max
VDDEXT = 2.5/3.3 V
Min
Max
Unit
tECOLH
tECOLL
tECRSH
tECRSL
COL Pulse Width High
COL Pulse Width Low
CRS Pulse Width High
CRS Pulse Width Low
tETxCLK x 1.5
tERxCLK x 1.5
tETxCLK x 1.5
tERxCLK x 1.5
tETxCLK x 1.5
tETxCLK x 1.5
tETxCLK x 1.5
ns
tERxCLK x 1.5
tETxCLK x 1.5
ns
tERxCLK x 1.5
tETxCLK x 1.5
ns
tETxCLK x 1.5
ns
1 MII/RMII asynchronous signals are COL and CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to
both the ETxCLK and the ERxCLK, and the COL input must have a minimum pulse width high or low at least 1.5 times the period of the slower of the two clocks.
2 The asynchronous CRS input is synchronized to the ETxCLK, and the CRS input must have a minimum pulse width high or low at least 1.5 times the period of ETxCLK.
Table 55. 10/100 Ethernet MAC Controller Timing: MII Station Management
ADSP-BF522/524/526 ADSP-BF523/525/527
Parameter1
VDDEXT =
1.8 V
Min Max
VDDEXT =
2.5/3.3 V
Min Max
VDDEXT =
1.8 V
Min Max
VDDEXT =
2.5/3.3 V
Min Max Unit
tMDIOS
tMDCIH
tMDCOV
tMDCOH
MDIO Input Valid to MDC Rising Edge (Setup)
11.5
11.5
10
MDC Rising Edge to MDIO Input Invalid (Hold)
11.5
11.5
10
MDC Falling Edge to MDIO Output Valid
25
25
25
MDC Falling Edge to MDIO Output Invalid (Hold)
–1
–1
–1
10
ns
10
ns
25
ns
–1
ns
1 MDC/MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. MDC is an output clock whose minimum period is programmable as a multiple
of the system clock SCLK. MDIO is a bidirectional data line.
ERx_CLK
tERXCLKW
tERXC LK
ERxD3-0
ERxDV
ERxER
MII TxCLK
ETxD3-0
ETxEN
tERXCLKIS
tERXCLKIH
Figure 35. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
tETXCLKW
tETXCLK
tETXCLKOH
tETXCLKOV
Figure 36. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
Rev. PrG | Page 61 of 80 | February 2009
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