ADSP-BF526BBCZ-4AX View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADSP-BF526BBCZ-4AX Datasheet PDF : 80 Pages
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Preliminary Technical Data
ADSP-BF522/523/524/525/526/527
JTAG Test And Emulation Port Timing
Table 56 and Figure 41 describe JTAG port operations.
Table 56. JTAG Port Timing
Parameter
VDDEXT = 1.8 V
Min
Max
VDDEXT = 2.5/3.3 V
Min
Max
Unit
Timing Parameters
tTCK
TCK Period
20
tSTAP
TDI, TMS Setup Before TCK High
4
tHTAP
TDI, TMS Hold After TCK High
4
tSSYS
System Inputs Setup Before TCK High1
12
tHSYS
System Inputs Hold After TCK High1
5
tTRSTW
TRST Pulse Width2 (measured in TCK cycles)
4
Switching Characteristics
20
ns
4
ns
4
ns
12
ns
5
ns
4
TCK
tDTDO
tDSYS
TDO Delay from TCK Low
System Outputs Delay After TCK Low3
10
10
ns
12
12
ns
1 System Inputs = DATA15–0, ARDY, SCL, SDA, PF15–0, PG15–0, PH15–0, TCK, TRST, RESET, NMI, BMODE3–0.
2 50 MHz Maximum
3 System Outputs = DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, PF15–0, PG15–0, PH15–0,
TDO, EMU.
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
tTCK
tSTAP
tHTAP
tDTDO
tSSYS
tHSYS
tDSYS
Figure 41. JTAG Port Timing
Rev. PrG | Page 63 of 80 | February 2009
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