ADSP-BF526BBCZ-4AX View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-BF526BBCZ-4AX

Blackfin® Embedded Processor

Analog Devices 

Preliminary Technical Data

TEST CONDITIONS

All timing parameters appearing in this data sheet were mea-

sured under the conditions described in this section. Figure 57

shows the measurement point for AC measurements (except

output enable/disable). The measurement point VMEAS is

VDDEXT/2 or VDDMEM/2 for VDDEXT/VDDMEM (nominal) = 1.8 V/2.5

V/3.3 V.

INPUT

OR

OUTPUT

VMEAS

VM EA S

Figure 57. Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)

Output Enable Time Measurement

Output balls are considered to be enabled when they have made

a transition from a high impedance state to the point when they

start driving.

The output enable time tENA is the interval from the point when

a reference signal reaches a high or low voltage level to the point

when the output starts driving as shown on the right side of

Figure 58.

tDIS

VOH

(MEASURED)

VOL

(MEASURED)

REFERENCE

SIGNAL

tDIS_MEASURED

tENA

VOH (MEASURED) ؊ ⌬V

VOL (MEASURED) + ⌬V

tDECAY

tENA _MEASURED

VOH(MEASURED)

VTRIP(HIGH)

VTRIP(LOW)

VOL(MEASURED)

tTRIP

OUTPUT STOPS DRIVING

OUTPUT STARTS DRIVING

HIGH IMPEDANCE STATE

Figure 58. Output Enable/Disable

The time tENA_MEASURED is the interval, from when the reference

signal switches, to when the output voltage reaches VTRIP(high)

or VTRIP(low). For VDDEXT/VDDMEM (nominal) = 1.8V, VTRIP

(high) is 1.05V, and VTRIP (low) is 0.75V. For VDDEXT/VDDMEM

(nominal) = 2.5V, VTRIP (high) is 1.5V and VTRIP (low) is 1.0V.

For VDDEXT/VDDMEM (nominal) = 3.3V, VTRIP (high) is 1.9V, and

VTRIP (low) is 1.4V. Time tTRIP is the interval from when the out-

put starts driving to when the output reaches the VTRIP(high) or

VTRIP(low) trip voltage.

Time tENA is calculated as shown in the equation:

tENA = tENA_MEASURED – tTRIP

If multiple balls (such as the data bus) are enabled, the measure-

ment value is that of the first ball to start driving.

ADSP-BF522/523/524/525/526/527

Output Disable Time Measurement

Output balls are considered to be disabled when they stop driv-

ing, go into a high impedance state, and start to decay from their

output high or low voltage. The output disable time tDIS is the

difference between tDIS_MEASURED and tDECAY as shown on the left

side of Figure 58.

tDIS = tDIS_MEASURED – tDECAY

The time for the voltage on the bus to decay by ΔV is dependent

on the capacitive load CL and the load current IL. This decay

time can be approximated by the equation:

tDECAY = (CLΔV) ⁄ IL

The time tDECAY is calculated with test loads CL and IL, and with

ΔV equal to 0.25 V for VDDEXT/VDDMEM (nominal) = 2.5 V/3.3 V

and 0.15 V for VDDEXT/VDDMEM (nominal) = 1.8V.

The time tDIS_MEASURED is the interval from when the reference

signal switches, to when the output voltage decays ΔV from the

measured output high or output low voltage.

Example System Hold Time Calculation

To determine the data output hold time in a particular system,

first calculate tDECAY using the equation given above. Choose ΔV

to be the difference between the processor’s output voltage and

the input threshold for the device requiring the hold time. CL is

the total bus capacitance (per data line), and IL is the total leak-

age or three-state current (per data line). The hold time will be

tDECAY plus the various output disable times as specified in the

Timing Specifications on Page 38 (for example tDSDAT for an

SDRAM write cycle as shown in SDRAM Interface Timing on

Page 44).

Rev. PrG | Page 67 of 80 | February 2009

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