ADSP-BF526BBCZ-4AX View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

ADSP-BF526BBCZ-4AX

Blackfin® Embedded Processor

Analog Devices 

ADSP-BF522/523/524/525/526/527

Capacitive Loading

Output delays and holds are based on standard capacitive loads

of an average of 6 pF on all balls (see Figure 59). VLOAD is equal

to (VDDEXT/VDDMEM) /2. The graphs of Figure 60 through

Figure 71 show how output rise time varies with capacitance.

The delay and hold specifications given should be derated by a

factor derived from these figures. The graphs in these figures

may not be linear outside the ranges shown.

VLOAD

50:

70:

50:

4pF

2pF

400:

TESTER PIN ELECTRONICS

45:

0.5pF

T1

DUT

OUTPUT

ZO = 50:(impedance)

TD = 4.04 r 1.18 ns

NOTES:

THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED

FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE

EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR

LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.

ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN

SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE

EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.

Figure 59. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

Preliminary Technical Data

Rev. PrG | Page 68 of 80 | February 2009

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