AD9775EB View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9775EB Datasheet PDF : 48 Pages
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AD9775
MODE CONTROL (VIA SPI PORT)
Table I. Mode Control via SPI Port
(Default Values Are Highlighted)
Address Bit 7
00h
SDIO
Bidirectional
0 = Input
1 = I/O
Bit 6
LSB, MSB First
0 = MSB
1 = LSB
01h
Filter
Filter
Interpolation
Interpolation
Rate
Rate
(1×, 2×, 4×, 8×) (1×, 2×, 4×, 8×)
Bit 5
Bit 4
Bit 3
Bit 2
Software Reset on
Logic “1”
Sleep Mode
Logic “1” shuts down
the DAC output
currents.
Power-Down Mode
Logic “1” shuts down
all digital and analog
functions.
1R/2R Mode
DAC output current set
by one or two external
resistors.
0 = 2R, 1 = 1R
Modulation
Mode
(None, fS/2,
fS/4, fS/8)
Modulation Mode
(None, fS/2, fS/4, fS/8)
0 = No Zero Stuffing
on Interpolation
Filters, Logic “1”
enables zero stuffing.
1 = Real Mix Mode
0 = Complex
Mix Mode
02h
0 = Signed Input 0 = Two Port Mode DATACLK Driver DATACLK Invert
Data
1 = One Port Mode
Strength
0 = No Invert
1 = Unsigned
1 = Invert
03h
ONEPORTCLK Invert
0 = No Invert
1 = Invert
04h
0 = PLL OFF
0 = Automatic
1 = PLL ON
Charge Pump Control
1 = Programmable
PLL Charge Pump
Control
05h
IDAC Fine Gain IDAC Fine Gain
Adjustment
Adjustment
IDAC Fine Gain IDAC Fine Gain
Adjustment
Adjustment
IDAC Fine Gain
Adjustment
IDAC Fine Gain
Adjustment
06h
IDAC Coarse Gain
IDAC Coarse Gain
Adjustment
Adjustment
07h
IDAC Offset
IDAC Offset
Adjustment Bit 9 Adjustment Bit 8
IDAC Offset
IDAC Offset
Adjustment Bit 7 Adjustment Bit 6
IDAC Offset
Adjustment Bit 5
IDAC Offset
Adjustment Bit 4
08h
IDAC IOFFSET
Direction
0 = IOFFSET
on IOUTA
1 = IOFFSET on
IOUTB
09h
QDAC Fine Gain QDAC Fine Gain
Adjustment
Adjustment
QDAC Fine Gain QDAC Fine Gain
Adjustment
Adjustment
QDAC Fine Gain
Adjustment
QDAC Fine Gain
Adjustment
0Ah
QDAC Coarse
QDAC Coarse
Gain Adjustment
Gain Adjustment
0Bh
QDAC Offset
QDAC Offset
Adjustment Bit 9 Adjustment Bit 8
QDAC Offset
QDAC Offset
Adjustment Bit 7 Adjustment Bit 6
QDAC Offset
Adjustment Bit 5
QDAC Offset
Adjustment Bit 4
0Ch
0Dh
QDAC IOFFSET
Direction
0 = IOFFSET
on IOUTA
1 = IOFFSET
on IOUTB
Version Register
Version Register
Bit 1
PLL_LOCK
Indicator
0 = e–j
1 = e+j
IQSEL Invert
0 = No Invert
1 = Invert
PLL Divide
(Prescaler) Ratio
PLL Charge Pump
Control
IDAC Fine Gain
Adjustment
IDAC Coarse Gain
Adjustment
IDAC Offset
Adjustment Bit 3
IDAC Offset
Adjustment Bit 1
QDAC Fine Gain
Adjustment
QDAC Coarse
Gain Adjustment
QDAC Offset
Adjustment Bit 3
QDAC Offset
Adjustment Bit 1
Version Register
Bit 0
DATACLK/
PLL_LOCK
Select
0 = PLLLOCK
1 = DATACLK
Q First
0 = I First
1 = Q First
PLL Divide
(Prescaler) Ratio
PLL Charge Pump
Control
IDAC Fine Gain
Adjustment
IDAC Coarse Gain
Adjustment
IDAC Offset
Adjustment Bit 2
IDAC Offset
Adjustment Bit 0
QDAC Fine Gain
Adjustment
QDAC Coarse
Gain Adjustment
QDAC Offset
Adjustment Bit 2
QDAC Offset
Adjustment Bit 0
Version Register
REV. 0
–13–
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