STLC5464 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STLC5464

MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED

STMicroelectronics 

STLC5464

II - BLOCK DIAGRAM

The top level functionalities of Multi-HDLC appear on the general block diagram.

Figure 1 : General Block Diagram

DIN6 26

DIN7 27

DIN8 28

25 24 23 22 21 20

GCI1

GCI0

0

1 SWITCHING MATRIX 0

2

n x 64 kb/s

1

3

2

4

3

5

4

6 Pseudo

Random

7

Sequence

Analyser

Pseudo 5

Random 6

Sequence

Generator

7

D7

39 31 32 33 34 35

36

37

38 12 10 13 11

GCI0

GCI1

V10

CLOCK

SELECTION

To

Internal

Circuit

18 FSCV*

17 FSCG

9 DCLK

16 FS

V10

TIME SLOT ASSIGNER FOR MULTIHDLC

5 CB

VCX IN 7

VCX OUT 8

XTAL1 2

XTAL2 3

WDO 4

COUNTER

GCI CHANNEL DEFINITION

XTAL

WATCHDOG

32 Rx HDLC

with Adress

Recognition

32 Rx DMAC

16 Rx

C/I

16 Rx

MON

16 Tx

C/I

16 Tx

MON

32 Tx HDLC

with CSMA CR

for Content. Bus

32 Tx DMAC

Rx Rx Tx Tx

C/I MON C/I MON

INTERRUPT

CONTROLLER

6 EC

49 INT0

50 INT1

µP Bus

µP

INTERFACE

Internal Bus

BUS ARBITRATION

There are :

- The switching matrix,

- The time slot assigner,

- The 32 HDLC transmitters with associated DMA

controllers,

- The 32 HDLC receivers with associated DMA

controllers,

- The 16 Command/Indicate and Monitor Channel

transmitters belonging to two General Compo-

nent Interfaces(GCI),

RAM

INTERFACE

RAM

Bus

STLC5464

- The 16 Command/Indicate and Monitor Channel

receivers belonging to two General Component

Interfaces (GCI),

- The memory interface,

- The microprocessor interface,

- The bus arbitration,

- The clock selection and time synchronization

function,

- The interrupt controller,

- The watchdog,

14/83

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