STLC5464 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STLC5464

MULTI-HDLC WITH n x 64 SWITCHING MATRIX ASSOCIATED

STMicroelectronics 

STLC5464

III - FUNCTIONAL DESCRIPTION (continued)

Figure 2 : Switching Matrix Data Path

DIN 0/7

Tx D7

HDLC

BIT SYNCHRO

DIN’ 0/7 D4/5 Rx

GCI

PRSG : Pseudo Random Sequence Generator

PRSA : Pseudo Random Sequence Analyzer From Connection

OTSV : Output Time Slot Validated

Memory

INS : Insert

CM : Connection Memory (from CMAR Register)

ME : Message Enable

IMTD : Increased Min Throughtput Delay

SGV : Sequence Generator Validated

SAV : Sequence Analyzer Validated

From SMCR Register

HDLCM

1

LOOP

1

S/P

PRSG

SGV

PSEUDO RANDOM

SEQUENCE

GENERATOR

211 - 1

Rec. O.152

IMTD

Sequence

Integrity

DATA

MEMORIES

64kb/s and

n x 64kb/s

1

A

CM 1

1

CM

(when Read)

CONNECTION

MEMORY

D

D

Sequence Integrity,

LOOP, PRSA, PRSG,

INS, OTSV

Internal

Bus

CMDR

Data

Register

CMAR

INS

1

PRSG

PRSA

SAV

Address

Register

ME

1

D0/7

Tx D4/5

GCI

GCIR

1

P/ S

D7

Rx

HDLC

PSEUDO RANDOM

SEQUENCE

ANALYZER

211 - 1

Rec. O.152

SFDR

Sequence Fault

Counter Register

BIT SYNCHRO

DOUT 0/7

From Connection Memory

OTSV (per channel)

From OMCR Register

OMV (per multiplex)

From Disable Pin

(for all multiplexes)

16/83

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