CL-PS7500FE データシートの表示（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

5.2.4 Read-Locked-Write

The IDC treats the Read-Locked-Write instruction as a special case. The read phase always forces a read

of external memory, regardless of whether the data is contained in the cache. The write phase is treated

as a normal write operation (and if the data is already in the cache, the cache is updated). Externally the

two phases are flagged as indivisible by asserting the LOCK signal.

5.3 IDC Enable/Disable and Reset

The IDC is automatically disabled and flushed on nRESET. Once enabled, cacheable read accesses

cause lines to be placed in the cache.

5.3.1 Enable the IDC

To enable the IDC, make sure that the MMU is enabled first by setting Control register, bit 0, then enable

the IDC by setting Control register, bit 2. The MMU and IDC can be simultaneously enabled with a single

control register write.

5.3.2 Disable the IDC

To disable the IDC, clear Control register, bit 2 and perform a flush by writing to the flush register.

5.4 Write Buffer (WB)

The ARM processor WB is provided to improve system performance. It can buffer up to 8 words of data,

and four independent addresses. It can be enabled or disabled through the W bit (bit 3) in the ARM pro-

cessor Control register and the buffer is disabled and flushed on reset.

The operation of the write buffer is further controlled by one bit, B or bufferable, stored in the Memory Man-

agement Page Tables. For this reason, to use the write buffer the MMU must be enabled.

The two functions may, however, be enabled simultaneously, with a single write to the Control register. For

a write to use the write buffer, both the W bit in the Control register, and the B bit in the corresponding

page table must be set.

5.4.1 Bufferable Bit

This bit controls whether a write operation may or may not use the write buffer. Typically main memory is

bufferable and I/O space unbufferable. The B bit can be configured for both pages and sections.

5.4.2 Write Buffer Operation

When the CPU performs a write operation, the translation entry for that address is inspected and the state

of the B bit determines the subsequent action. If the write buffer is disabled through the ARM processor

Control register, bufferable writes are treated in the same way as unbuffered writes.

Bufferable Write

If the write buffer is enabled and the processor performs a write to a bufferable area, the data is placed in

the write buffer at FCLK speeds and the CPU continues execution. The write buffer then performs the

external write in parallel. If the write buffer is full (either because there are already 8 words of data in the

buffer, or because there is no slot for the new address) then the processor is stalled until there is sufficient

space in the buffer.

36

IDC

ADVANCE DATA BOOK v2.0

June 1997

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