CL-PS7500FE データシートの表示（PDF） - Cirrus Logic

部品番号

コンポーネント説明

メーカー

CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

Unbufferable Writes

If the write buffer is disabled or the CPU performs a write to an unbufferable area, the processor is stalled

until the write buffer empties and the write completes externally. This process may require synchronization

and several external clock cycles.

Read-Locked Write

The write phase of a read-locked-write sequence is treated as an unbuffered write, even if it is marked as

buffered.

NOTE: A single write requires one address slot and one data slot in the write buffer; a sequential write of n words

requires one address slot and n data slots. The entire eight data slots in the buffer can be used as required.

So for instance there could be three non-sequential writes and one sequential write of 5 words in the buffer,

and the processor could continue as normal: a fifth write or a sixth word in the fourth write would stall the

processor until the first write is complete.

5.4.3 Enable the Write Buffer

To enable the WB, ensure the MMU is enabled by setting Control register, bit 0, then enable the write

buffer by setting Control register, bit 3. The MMU and write buffer can be enabled simultaneously with a

single write to the Control register.

5.4.4 Disable the Write Buffer

To disable the WB, clear the control register, bit 3.

NOTE: Any writes already in the write buffer completes normally.

5.5 Coprocessors

The on-chip FPA is a coprocessor and its operation are described later in this manual.

The ARM processor also has an internal coprocessor designated #15 for internal control of the device.

However, the CL-PS7500FE has no external coprocessor bus, so it is not possible to add further external

coprocessors to this device. All coprocessor operations, other than those implemented by the FPA, MRC,

or MCR to registers 0–7 on coprocessor #15, cause the undefined instruction trap to be taken.

June 1997

ADVANCE DATA BOOK v2.0

37

IDC

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