CL-PS7500FE データシートの表示（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

REGISTER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 WRITE 0

CONTROL

R S B 1 D PW C AM

2 WRITE

3 WRITE 15

5 READ

TRANSLATION TABLE BASE

DOMAIN ACCESS CONTROL

14 13 12 11 10 9

8

7

6

5

4

FAULT STATUS

0 0 00

3

2

DOMAIN

1

0

STATUS

5 WRITE

FLUSH TLB

6 READ

FAULT ADDRESS

6 WRITE

TLB PURGE ADDRESS

Figure 6-1. MMU Register Summary

6.1.1 Translation Table Base Register

The Translation Table Base register contains the physical address of the base of the translation table

maintained in main memory. Note that this base must reside on a 16-Kbyte boundary.

6.1.2 Domain Access Control Register

The Domain Access Control register consists of sixteen 2-bit fields, each defines the access permissions

for one of the sixteen domains (D[15:0]).

NOTE: The registers not shown are reserved and should not be used.

6.1.3 Fault Status Register

The Fault Status register indicates the domain and type of access being attempted when an abort

occurred. Bits 7:4 specify the accessed of the sixteen domains (D[15:0]) during a fault. Bits 3:1 indicate

the type of access being attempted. The encoding of these bits is different for internal and external faults

(as indicated by bit 0 in the register) and is shown in Table 6-4 on page 47. A write to this register flushes

the TLB.

6.1.4 Fault Address Register

The Fault Address register holds the virtual address of the access attempted when a fault occurred. A

write to this register causes the data written to be treated as an address and, if it is found in the TLB, the

entry is marked as invalid. (This operation is known as a TLB ‘purge’.) The Fault Status and Fault Address

registers are only updated for data faults, not for prefetch faults.

6.2 Address Translation

The MMU translates virtual addresses generated by the CPU into physical addresses to access external

memory, and also derives and checks the access permission. Translation information, consisting of both

the address translation data and the access permission data, resides in a translation table located in

physical memory. The MMU provides the logic needed to traverse this translation table, obtain

the translated address, and check the access permission.

June 1997

ADVANCE DATA BOOK v2.0

39

ARM PROCESSOR MMU

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