M25PE80-VMN6TP データシートの表示（PDF） - STMicroelectronics

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M25PE80-VMN6TP

8 Mbit, low-voltage, Page-Erasable Serial Flash memory with byte alterability, 50 MHz SPI bus, standard pinout

STMicroelectronics 

M25PE80

Memory organization

Table 5. Memory organization (continued)

Sector Subsector Address Range

Sector Subsector

31

1F000h 1FFFFh

15

1

16

10000h 10FFFh

4

0

3

2

1

0

Address Range

0F000h 0FFFFh

04000h

03000h

02000h

01000h

00000h

04FFFh

03FFFh

02FFFh

01FFFh

00FFFh

Figure 6. Block diagram

Reset

TSL or W

S

C

D

Q

Control Logic

High Voltage

Generator

I/O Shift Register

Address Register

and Counter

F0000h

256 Byte

Data Buffer

Status

Register

FFFFFh

Top 256 Pages can

be made read-only

by using the TSL pin(1)

Whole Memory Array can

be made read-only

on a 64 Kbyte or 4 Kbyte(1)

basis through the Lock

Registers

00000h

000FFh

256 Bytes (Page Size)

X Decoder

1. These features (in gray) are only available in the T7Y process.

AI13560

19/61

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