PSD412A2-C-90UI 데이터 시트보기 (PDF) - STMicroelectronics
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PSD412A2-C-90UI Datasheet PDF : 123 Pages
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PSD4XX Family
AC/DC Parameters – ZPLD Timing Parameters (ZPSD4XXV Versions)
(3.0 V ± 10%)
Asynchronous Clock Mode (3.0 V ± 10%, Note 1)
Symbol
Parameter
Conditions
-20
-25
ZPLD_TURBO
Min Max Min Max
OFF*
Unit
Maximum Frequency
External Feedback
1/(tSA + tCOA)
14.49
11.11
f MAXA
Maximum Frequency
1/(tS A+ tCO A–10)
Internal Feedback (fCNTA) (Note 1)
Maximum Frequency
Pipelined Data
1/(tCH + tCL)
16.95
31.25
12.50
18.52
t SA
Input Setup Time
Any Input
13
30
t HA
Input Hold Time
Any Input
13
30
t CHA Clock High Time
Any Input
25
27
t CLA Clock Low Time
Any Input
16
27
t COA Clock to Output Delay
Any Input to Port B
56
60
t ARD
Array Delay for Product
Term Expansion
Any Macrocell
33
35
tMINA Minimum Clock Period
1/fCNT
59
80
Add 20
0
0
0
Add 20
0
0
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
NOTE: 1. Only Port B has asynchronous outputs. Clock into macrocell Flip Flop is generated by a product term.
*If ZPLD_TURBO is off and the ZPLD is operating above 15 MHz, there is no need to add 20 ns to the timing parameters.
90
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