PSD412A2-C-90UI 데이터 시트보기 (PDF) - STMicroelectronics
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PSD412A2-C-90UI Datasheet PDF : 123 Pages
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PSD4XX Family
13.11 Microcontroller Interface – AC/DC Parameters (ZPSD4XXV Versions)
(3.0 V ± 10%)
Explanation of AC Symbols for Non ZPLD Timing.
Example:
t AVLX Time from Address Valid to ALE Invalid.
A – Address
C – Power Down
D– Input Data
E– E
H – Logic Level High
I – Interrupt
L – Logic Level Low or ALE
N – Reset
P – Port Signal
Q – Output Data
R – WR, UDS, LDS, DS, IORD, PSEN
S – Chip Select
T – R/W
t – Time
V – Valid
X – No Longer a Valid Logic Level
Z – Float
Read Timing (3.0 V ± 10%)
Symbol
Parameter
Conditions
-20
-25
EPROM_CMiser
Min Max Min Max
ON
Unit
tLVLX ALE or AS Pulse Width
30
30
0
ns
tAVLX Address Setup Time
(Note 3)
12
15
0
ns
tLXAX Address Hold Time
(Note 3)
12
17
0
ns
tAVQV Address Valid to Data Valid
(Note 3)
200
250
Add 20
ns
t SLQV CS Valid to Data Valid
200
275
Add 20
ns
t RLQV
RD to Data Valid 8/16-Bit Bus
RD to Data Valid 8-Bit Bus,
8031 Separate Mode
(Note 1)
(Note 2)
50
80
0
ns
57
90
0
ns
t RHQX RD Data Hold Time
(Note 1)
0
0
0
ns
tRLRH RD Pulse Width
(Note 1)
40
70
0
ns
tRHQZ RD to Data High-Z
(Note 1)
45
45
0
ns
tEHEL E Pulse Width
40
70
0
ns
tTHEH R/W Setup Time to Enable
20
15
0
ns
tELTL R/W Hold Time After Enable
0
0
0
ns
Address Input Valid to
In 16-Bit Data Bus
Mode (Note 4)
40
60
0
ns
tAVPV Address Output Delay
In 8-Bit Data Bus
Mode (Note 4)
50
60
0
ns
NOTES: 1. RD timing has the same timing as PSEN, DS, LDS, UDS signals.
2. RD and PSEN have the same timing for 8031 mode.
3. Any input used to select an internal PSD4XX function.
4. In multiplexed mode latched address generated from ADIO delay to address output on any Port.
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