CL-PS7500FE 데이터 시트보기 (PDF) - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

4. THE ARM PROCESSOR MACROCELL

The CL-PS7500FE contains a 32-bit RISC ARM processor, similar to the ARM710C macrocell. It has a

4-Kbyte cache, write buffer, and an MMU. The ARM processor macrocell offers high-level RISC perfor-

mance, yet its fully static design ensures minimal power consumption. This makes it ideal for incorporation

into the CL-PS7500FE. The CL-PS7500FE aims to make maximum use of the performance and flexibility

offered by the ARM processor.

This section describes the features of the ARM processor macrocell available to the user in its embedded

state within the CL-PS7500FE single-chip computer.

4.1 Architecture

The ARM processor architecture is based on RISC principles, and the instruction set and related decode

mechanism are greatly simplified compared with microprogrammed CISCs.

The mixed data and instruction cache, together with the write buffer, substantially raise the average exe-

cution speed and reduce the average amount of memory bandwidth required by the processor. This

allows the CL-PS7500FE bus structure to support DMA channels with minimal performance loss.

The MMU supports a conventional two-level page-table structure and a number of extensions, making it

ideal for embedded control, UNIX, and object-oriented systems.

4.2 Instruction Set

The instruction set comprises ten basic instruction types:

q Two instruction types make use of the on-chip ALU, barrel shifter, and multiplier to perform high-speed oper-

ations on the data in a bank of 31 registers, each 32 bits wide.

q Three classes of instruction control data transfers between memory and the registers:

— one optimized for flexibility of addressing,

— another for rapid context switching, and

— the third for swapping data.

q Two instructions control the flow and privilege level of execution.

q Three instruction types are dedicated to the control of coprocessors that allow the functionality of the instruc-

tion set to be extended in an open and uniform way; the on-chip FPA is one such processor.

However, the facility to add external coprocessors to the CL-PS7500FE is not available, and software emu-

lation of coprocessor activity is required if instructions, other than those for the on-chip FPA or control copro-

cessor #15, are to perform a defined function.

The ARM instruction set is a good target for compilers of many different high-level languages. Where

required for critical code segments, assembly code programming is also straightforward, unlike some

RISC processors that depend on sophisticated compiler technology to manage complicated instruction

interdependencies.

June 1997

ADVANCE DATA BOOK v2.0

33

THE ARM PROCESSOR MACROCELL

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