ML6461CS 데이터 시트보기 (PDF) - Micro Linear Corporation
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ML6461CS Datasheet PDF : 30 Pages
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ML6461
CLK
HSYNC
(output)
(0,0) or (0,1) or (1,0) or (1,1) via (SEL_HSYNC1, SEL_HSYNC0)
(0,0)
(0,1)
(1,0)
(1,1)
YCrCb
BL
BL
BL
Beginning
of Horizontal
Blanking
T
2T
3T
Q Clock Cycles
if ANALOG_HBLANK = 0
if ANALOG_HBLANK = 1
# of Clock Cycles, Q
if SELCCIR = 1 if SELCCIR = 0
244
214
252
214
BL
BL
BL
CB0
Y0
CR0
Y1
Figure 5. Pixel Synchronization. For Master Mode, Active Edge at Beginning of Horizontal Blanking.
(CBLANK = 0, SENSE_HSYNC = 0) (BL = Blanked Pixel)
CLK
HSYNC (output)
(0,0) or (0,1) or (1,0) or (1,1) via (SEL_HSYNC1, SEL_HSYNC0)
(0,0)
(0,1)
(1,0)
(1,1)
YCrCb
BL
BL
BL
BL
BL
BL
CB0
Y0
CR0
Y1
Beginning
of Horizontal
Blanking
T
2T
3T
Q Clock Cycles
if ANALOG_HBLANK = 0
if ANALOG_HBLANK = 1
# of Clock Cycles, Q
if SELCCIR = 1 if SELCCIR = 0
244
214
252
214
Figure 5a. Pixel Synchronization. For Master Mode, Active Edge at Beginning of Horizontal Blanking.
(CBLANK = 0, SENSE_HSYNC = 1) (BL = Blanked Pixel)
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