ML6461CS 데이터 시트보기 (PDF) - Micro Linear Corporation
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ML6461CS Datasheet PDF : 30 Pages
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ML6461
FUNCTIONAL DESCRIPTION (Continued)
PHASE ERROR INPUT AND CHROMA SUBCARRIER
CORRECTION (FOR OVERLAY APPLICATIONS)
The chroma oscillator phase and frequency can be altered
in real time using the PHERR input. This pin can receive a
signal that corrects chroma variations for signals with
unstable time base errors. To properly initialize the ML6461
overlay interface, follow the steps below:
1. Set the control register bit OVERLAY_ON (B16) to logical
0. This will disable the interface and let the chroma
subcarrier oscillator run free.
2. Force the PHERR input to logical 0 (idle state) for at least
128 clock cycles and set the control register bit
OVERLAY_ON (B16) to logical 1 while PHERR is held
low. This will enable the interface.
3. Clock in the startup code of 101 and then serially (LSB
first) the 32-bit frequency value FSQ (frequency number)
followed by the 12-bit phase value PHQ (phase number).
Equation 1 calculates color subcarrier frequency:
FSC
=
FSQ
232
× FCLK
2
(1)
Where FCLK is the 27 MHz (or 24.54MHz) as the system
clock and FSC is the actual color subcarrier frequency.
4. To turn-off the interface and have the subcarrier oscillator
on free run, the control register bit OVERLAY_ON (B16)
must be reset to logical 0.
5. When this function is disabled, the internal default values
for FSQ are:
0X 43E0F7AD for CCIR656
0X 4AAAAA0B for Square Pixel.
CLOSED CAPTIONING
The ML6461 enables the transmission of VBI Closed
Caption codes on lines 21 and 284. To properly initialize
the closed caption interface, follow the steps below:
1. Set the control register bits CC_21 (B19) and CC_284
(B18) to logical 0. This will disable transmission of
Closed Caption (CC) data.
2. For each line, write the two byte closed caption (CC)
data, including the parity bit, to the CC data register
through the serial bus interface. Note that the ML6461
does not generate the parity bits. If only line 21 or line
284 transmission is desired, only two bytes of data are
needed per frame. If both lines are used for
transmission, then four bytes (the first two bytes
corresponding to line 21) must be entered all at once
into the closed caption data register (CC register).
3. Set the control register bits CC_21 (B19) and/or CC_284
(B18) to logical 1. This will enable CC transmission at
the desired lines.
18
4. Repeat STEP 2 as many times as needed.
Note that CC data is transmitted once (twice if both lines
are used) per frame. Hence attempts to transmit CC data
at a rate faster than four bytes per frame will result on
overwriting some of the previously entered data before the
encoder has a chance to transmit. To prevent overwriting
of data, the CC controller and the ML6461 need to be
synchronized. This can be easily achieved by polling the
vertical blanking pulse and updating the CC data registers
once per frame during the vertical blanking interval or any
appropriate interval which does not include lines 21 or
284. Also, active video information is blanked on lines for
which closed caption transmission is enabled. Note that
the last data written on the CC registers will be sent
continuously once per frame (on line 21 or line 284
depending on the mode chosen) until the interface is
disabled. Figure 13 shows Closed Caption waveforms for
various modes. See Table 7 and Figure 17 for more Closed
Caption information. Note that parity bits A7, A15, A23,
and A31 must be generated externally.
PROGRAMMING INTERFACE
The ML6461 can be programmed either through PRESET
modes or through SERIAL BUS mode.
REGISTER INFORMATION
See Table 6 for ML6461 register summary information.
CONTROL REGISTERS: DESCRIPTION OF FUNCTION
Reserved, B31:B30 These bits are reserved and must be
set to 1 (B31=B30=1) for normal operation.
CBLANK, B29 In master mode, and internal slave mode,
a composite blanking signal is also available thru the
HSYNC pin. This can be activated via the CBLANK bit
(B29=1). The polarity of the composite blanking signal is
programmable thru the SENSE_HSYNC bit (B15). When
the SENSE_HSYNC bit is set (B15=1), the ML6461 will
output a logic 0 at the HSYNC pin during the pixels
which are blanked. Conversely, when the
SENSE_HSYNC bit is cleared (B15=0), the ML6461 will
output a logic 1 at the HSYNC pin during the pixels
which are blanked. Consequently, the YCRCB<7:0>
inputs will be ignored and a constant blanking level will
be output to the analog channels YOUT, COUT, and
CVOUT. The operation of the VSYNC and FIELD pins are
not affected by the settings of CBLANK and
SENSE_HSYNC.
SLAVE/MASTER, B28 This bit determines if device
operates in master or slave modes. Configuration of
HSYNC, VSYNC and FIELD are determined upon
selection of this bit. Table 3 provides a summary of Slave /
Master modes. When this bit is set (B28=1), the ML6461
is in slave mode. When this bit is cleared (B28=0), the
ML6461 is in master mode. Special note for slave modes:
this bit (B28) along with the SLAVE_MODE bit (B26)
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