STPCI2 查看數據表（PDF） - STMicroelectronics

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STPCI2

X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS

STMicroelectronics 

STPC® ATLAS

CAS#[1:0] Column Address Strobe. There are two

active-low column address strobe output signals.

The CAS# signals drive the memory devices

directly without any external buffering.

the STPC Atlas is the target of the current PCI

transaction or when no other device asserts

DEVSEL# prior to the subtractive decode phase of

the current PCI transaction.

MWE# Write Enable. Write enable specifies PAR Parity Signal Transactions. This is the parity

whether the memory access is a read (MWE# = H) signal of the PCI bus. This signal is used to

or a write (MWE# = L). This single write enable guarantee even parity across AD[31:0],

controls all DRAMs. The MWE# signals drive the CBE[3:0]#, and PAR. This signal is driven by the

memory devices directly without any external master during the address phase and data phase

buffering.

of write transactions. It is driven by the target

during data phase of read transactions. (Its

2.2.3. PCI INTERFACE

assertion is identical to that of the AD bus delayed

by one PCI clock cycle)

AD[31:0] PCI Address/Data. This is the 32-bit

multiplexed address and data bus of the PCI. This PERR# Parity Error

bus is driven by the master during the address

phase and data phase of write transactions. It is SERR# System Error. This is the system error

driven by the target during data phase of read signal of the PCI bus. It may, if enabled, be

transactions.

t(s) PBE[3:0]# Bus Commands/Byte Enables. These

are the multiplexed command and Byte enable

c signals of the PCI bus. During the address phase

u they define the command and during the data

d phase they carry the Byte enable information.

ro These pins are inputs when a PCI master other

than the STPC Atlas owns the bus and outputs

P when the STPC Atlas owns the bus.

te FRAME# Cycle Frame. This is the frame signal of

le the PCI bus. It is an input when a PCI master owns

o the bus and is an output when STPC Atlas owns

s the PCI bus.

Ob TRDY# Target Ready. This is the target ready

- signal of the PCI bus. It is driven as an output

) when the STPC Atlas is the target of the current

t(s bus transaction. It is used as an input when STPC

Atlas initiates a cycle on the PCI bus.

uc IRDY# Initiator Ready. This is the initiator ready

d signal of the PCI bus. It is used as an output when

ro the STPC Atlas initiates a bus cycle on the PCI

bus. It is used as an input during the PCI cycles

P targeted to the STPC Atlas to determine when the

te current PCI master is ready to complete the

current transaction.

ole STOP# Stop Transaction. STOP# is used to

s implement the disconnect, retry and abort protocol

bof the PCI bus. It is used as an input for the bus

Ocycles initiated by the STPC Atlas and is used as

asserted for one PCI clock cycle if target aborts a

STPC Atlas initiated PCI transaction. Its assertion

by either the STPC Atlas or by another PCI bus

agent will trigger the assertion of NMI to the host

CPU. This is an open drain output.

LOCK# PCI Lock. This is the lock signal of the PCI

bus and is used to implement the exclusive bus

operations when acting as a PCI target agent.

PCI_REQ#[2:0] PCI Request. These pins are the

three external PCI master request pins. They

indicates to the PCI arbiter that the external agents

desire use of the bus.

PCI_GNT#[2:0] PCI Grant. These pins indicate

that the PCI bus has been granted to the master

requesting it on its PCI_REQ#.

PCI_INT#[3:0] PCI Interrupt Request. These are

the PCI bus interrupt signals. They are to be

encoded before connection to the STPC Atlas

using ISACLK and ISACLKX2 as the input

selection strobes.

2.2.4. ISA BUS INTERFACE

LA[23:17] Unlatched Address. These unlatched

ISA Bus pins address bits 23-17 on 16-bit devices.

When the ISA bus is accessed by any cycle

initiated from the PCI bus, these pins are in output

mode. When an ISA bus master owns the bus,

these pins are tristated.

an output when a PCI master cycle is targeted to SA[19:0] Unlatched Address. These are the 20

the STPC Atlas.

low bits of the system address bus of ISA. These

pins are used as an input when an ISA bus master

DEVSEL# Device Select. This signal is used as an owns the bus and are outputs at all other times.

input when the STPC Atlas initiates a bus cycle on

the PCI bus to determine if a PCI slave device has SD[15:0] I/O Data Bus (ISA). These are the

decoded itself to be the target of the current external ISA databus pins.

transaction. It is asserted as an output either when

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