STPCI2 查看數據表（PDF） - STMicroelectronics

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STPCI2

X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS

STMicroelectronics 

STPC® ATLAS

VSYNC Vertical Synchronisation Pulse. This is the - odd (not-top) field: LOW level

vertical synchronization signal from the VGA - even (bottom) field: HIGH level

controller.

2.2.11. TFT INTERFACE SIGNALS

HSYNC Horizontal Synchronisation Pulse. This is

the horizontal synchronization signal from the The TFT (Thin Film Transistor) interface converts

VGA controller.

signals from the CRT controller into control signals

for an external TFT Flat Panel. The signals are

VREF_DAC DAC Voltage reference. This pin is an listed below.

input driving the digital to analog converters. This

allows an external voltage reference source to be TFTFRAME, Vertical Sync. pulse Output.

used.

TFTLINE, Horizontal Sync. Pulse Output.

RSET Resistor Current Set. This is the reference

current input to the RAMDAC. Used to set the full- TFTDE, Data Enable.

scale output of the RAMDAC.

TFTR5-0, Red Output.

COMP Compensation. This is the RAMDAC

compensation pin. Normally, an external capacitor TFTG5-0, Green Output.

(typically 10nF) is connected between this pin and

) VDD to damp oscillations.

t(s DDC[1:0] Direct Data Channel Serial Link. These

c bidirectional pins are connected to CRTC register

u 3Fh to implement DDC capabilities. They conform

d to I2C electrical specifications, they have open-

ro collector output drivers which are internally

connected to VDD through pull-up resistors.

te P They can instead be used for accessing I²C

devices on board. DDC1 and DDC0 correspond to

le SCL and SDA respectively.

so 2.2.10. VIDEO INTERFACE

Ob VCLK Pixel Clock Input.This signal is used to

- synchronise data being transferred from an

) external video device to either the frame buffer, or

t(s alternatively out the TV output in bypass mode.

This pin can be sourced from STPC if no external

c VCLK is detected, or can be input from an external

u video clock source.

rod VIN[7:0] YUV Video Data Input ITU-R 601 or 656.

Time multiplexed 4:2:2 luminance and

P chrominance data as defined in ITU-R Rec601-2

te and Rec656 (except for TTL input levels). This bus

typically carries a stream of Cb,Y,Cr,Y digital video

le at VCLK frequency, clocked on the rising edge (by

o default) of VCLK.

bs VCS Line synchronisation Input. This is the

Ohorizontal synchronisation of the incomming

TFTB5-0, Blue Output.

TFTENVDD, Enable VDD of Flat Panel.

TFTENVCC, Enable VCC of Flat Panel.

PWM PWM Back-Light Control. This PWM is

clocked by the PCI clock.

TFTDCLK, Dot clock for the Flat Panel.

2.2.12. USB INTERFACE

OC OVER CURRENT DETECT This signal is

used to monitor the status of the USB power

supply lines of both devices. USB port are

disabled when OC signal is asserted.

USBDPL0, USBDMNS0 UNIVERSAL SERIAL

BUS DATA 0 This signal pair comprises the

differential data signal for USB port 0.

USBDPL1, USBDMNS1 UNIVERSAL SERIAL

BUS PORT 1 This signal pair comprises the

differential data signal for USB port 1.

POWERON USB power supply lines

2.2.13. SERIAL INTERFACE

RXD0, RXD1 Serial Input. Data is clocked in using

RCLK/16.

CCIR601 video.

TXD0, TXD1 Serial Output. Data is clocked out

The signal is synchronous to rising edge of VCLK. using TCLK/16 (TCLK=BAUD#).

ODD_EVEN Frame Synchronisation Output. This

is the vertical synchronisation of the incomming

CCIR601 video.

The signal is synchronous to rising edge of VCLK.

The default polarity for this pin is:

DCD0#, DCD1# Input Data carrier detect.

RI0#, RI1# Input Ring indicator.

DSR0#, DSR1# Input Data set ready.

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