STPCI2 查看數據表（PDF） - STMicroelectronics
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STPCI2 Datasheet PDF : 108 Pages
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STPC® ATLAS
RMRTCCS# ROM/Real Time clock chip select. IORD# I/O Read. This output is used with REG# to
This pin is a multi-function pin. This signal is gate I/O read data from the PC Card, (only when
asserted if a ROM access is decoded during a REG# is asserted).
memory cycle. It should be combined with MEMR#
or MEMW# signals to properly access the ROM. IOWR# I/O Write. This output is used with REG#
During an IO cycle, this signal is asserted if access to gate I/O write data from the PC Card, (only
to the Real Time Clock (RTC) is decoded. It should when REG# is asserted).
be combined with IOR# or IOW# signals to
properly access the real time clock.
WP Write Protect. This input indicates the status of
the Write Protect switch (if fitted) on memory PC
IRQ_MUX[3:0] Multiplexed Interrupt Request. Cards (asserted when the switch is set to write
These are the ISA bus interrupt signals. They are protect).
to be encoded before connection to the STPC
Atlas using ISACLK and ISACLKX2 as the input BVD1, BVD2 Battery Voltage Detect. These
selection strobes.
inputs will be generated by memory PC Cards that
Note that IRQ8B, which by convention is include batteries and are an indication of the
connected to the RTC, is inverted before being condition of the batteries. BVD1 and BVD2 are
sent to the interrupt controller, so that it may be kept asserted high when the battery is in good
connected directly to the IRQ# pin of the RTC.
condition.
) ISAOE# Bidirectional OE Control. This signal
t(s controls the OE signal of the external transceiver
that connects the IDE DD bus and ISA SA bus.
uc KBCS# Keyboard Chip Select. This signal is
d asserted if a keyboard access is decoded during a
ro I/O cycle.
P ZWS# Zero Wait State. This signal, when asserted
te by addressed device, indicates that current cycle
can be shortened.
ole DACK_ENC[2:0] DMA Acknowledge. These are
s the ISA bus DMA acknowledge signals. They are
b encoded by the STPC Atlas before output and
O should be decoded externally using ISACLK and
- ISACLKX2 as the control strobes.
t(s) DREQ_MUX[1:0] ISA Bus Multiplexed DMA
Request. These are the ISA bus DMA request
c signals. They are to be encoded before connection
u to the STPC Atlas using ISACLK and ISACLKX2
d as the input selection strobes.
ro TC ISA Terminal Count. This is the terminal count
P output of the DMA controller and is connected to
te the TC line of the ISA bus. It is asserted during the
last DMA transfer, when the Byte count expires.
ole 2.2.5. PCMCIA INTERFACE
bs RESET Card Reset. This output forces a hard
Oreset to a PC Card.
READY#/BUSY#/IREQ# Ready/busy/Interrupt
request. This input is driven low by memory PC
Cards to signal that their circuits are busy
processing a previous write command.
WAIT# Bus Cycle Wait. This input is driven by the
PC Card to delay completion of the memory or I/O
cycle in progress.
OE# Output Enable. OE# is an active low output
which is driven to the PC Card to gate Memory
Read data from memory PC Cards.
WE#/PRGM# Write Enable. This output is used by
the host for gating Memory Write data. WE# is also
used for memory PC Cards that have
programmable memory.
REG# Attribute Memory Select. This output is
inactive (high) for all normal accesses to the Main
Memory of the PC Card. I/O PC Cards will only
respond to IORD# or IOWR# when REG# is active
(low). Also see Section 2.2.7.
CD1#, CD2# Card Detect. These inputs provide
for the detection of correct card insertion. CD#1
and CD#2 are positioned at opposite ends of the
connector to assist in the detection process.
These inputs are internally grounded on the PC
Card therefore they will be forced low whenever a
card is inserted in a socket.
CE1#, CE2# Card Enable. These are active low
output signals provided from the PCIC. CE#1
A[25:0] Address Bus. These are the 25 low bits of enables even Bytes, CE#2 odd Bytes.
the system address bus of the PCMCIA bus.
These pins are used as an input when an PCMCIA ENABLE# Enable. This output is used to activate/
bus owns the bus and are outputs at all other select a PC Card socket. ENABLE# controls the
times.
external address buffer logic.C card has been
detected (CD#1 and CD#2 = '0').
D[15:0] I/O Data Bus (PCMCIA). These are the
external PCMCIA databus pins.
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