STPCD01 查看數據表（PDF） - STMicroelectronics

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STPCD01

PC Compatible Embedded Microprocessor

STMicroelectronics 

STRAP OPTION

Memory

Data Refer to

Lines

MD38

-

MD39

-

MD40

-

MD41

-

MD42

-

MD43

-

Designation

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Location

-

-

-

-

-

-

Actual

Settings

-

-

-

-

-

-

Set to ’0’

-

-

-

-

-

-

Set to ’1’

-

-

-

-

-

-

Note; Setting of Strap Options MD [15:2] have no

effect on the DRAM Controller but are purely

meant for software issues. i.e. Readable in a reg-

ister.

3.1 Power on strap registers description

3.1.2 Strap register 1 Index 4Bh (Strap1)

Bits 7-0; This register reflect the status of pins

MD[15:8] respectively. They are expected to be

connected on the system board to the SIMM con-

figuration pins as follows:

3.1.1 Strap register 0 Index 4Ah (Strap0)

Bits 7-0; This register reflect the status of pins

MD[7:0] respectively. They are expected to be

connected on the system board to the SIMM con-

figuration pins as follows:

Bit Sampled

Bit 7

Bits 6-5

Bit 4

Bits 3-2

Bit 1

Bit 0

Description

SIMM 0 DRAM type

SIMM 0 speed

SIMM 1 DRAM type:

SIMM 1 speed

Reserved

Reserved

Note that the SIMM speed and type information

read here is meant only for the software and is not

used by the hardware. The software must pro-

gram the Host and graphics dram controller con-

figuration registers appropriately based on these

bits.

This register defaults to the values sampled on

MD[7:0] pins after reset.

Bit Sampled

Bit 7

Bits 6-5

Bit 4

Bits 3-2

Bit 1

Bit 0

Description

SIMM 2 DRAM type

SIMM 2 speed

SIMM 3 dram type

SIMM 3 speed

Reserved

Reserved

Note that the SIMM speed and type information

read here is meant only for the software and is not

used by the hardware. The software must pro-

gram the Host and graphics dram controller con-

figuration registers appropriately based on these

bits.

This register defaults to the values sampled on

MD[15:8] pins after reset.

3.1.3 Strap register 2 Index 4Ch (Strap2)

Bits 4-0; This register reflect the status of pins

MD[20:16] respectively.They are use by the chip

as follows:

Bit 4-2; Reserved.

Bit 1; This bit reflects the value sampled on

MD[17] pin and controls the PCI clock output as

follows:

0: PCI clock output = HCLK / 2

1: PCI clock output = HCLK / 3.

Bit 0; Reserved.

This register defaults to the values sampled on

MD[20:16] pins after reset.

28/48

Issue 1.7 - February 8, 2000

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