CL-PS7500FE 查看數據表（PDF） - Cirrus Logic

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CL-PS7500FE

System-on-a Chip for Internet Appliance

Cirrus Logic 

CL-PS7500FE

System-on-a-Chip for Internet Appliance

21.1.4 Clock Prescalars

76543210

X X X X XCM I

Each of the three main clock inputs CPUCLK, I_OCLK and MEMCLK has a selectable divide by 2 pres-

calar available within CL-PS7500FE to enable a guaranteed 50:50 mark-space ratio internal clock to be

produced using a higher frequency external oscillator. The internal clocks, referred to elsewhere in this

data book, are called FCLK, IOCK32, and MEMRFCK, respectively.

At power on reset, all the prescalars is set to divide by 2. Prescaling is controlled by the CLKCTL register

at address 0x0320003C, and there is one bit to enable or disable each divide by 2 prescalar as required:

C

CPUCLK divide control

M

MEMCLK divide control

I

I_OCLK divide control

Write

bit[2]

0

FCLK × 2 = CPUCLK

1

FCLK = CPUCLK

bit[1]

0

MEMRFCK × 2 = MEMCLK

1

MEMRFCK = MEMCLK

bit[0]

0

IOCK32 × 2 = I_OCLK

1

IOCK32 = I_OCLK

Read

return above value

Power on reset

set all to ‘0’, that is, divide by 2 clocks

21.1.5 Clocking Schemes

The simplest mode of operation of the CL-PS7500FE has all three of the main clocks driven by a single

32-MHz oscillator, with the prescalars set to Divide-by-1 mode. However, it is possible to increase the

speed of the memory and CPU clocks, noting that if this causes CPUCLK and MEMCLK frequencies to

be different, the SnA input must be set low for asynchronous operation. The I_OCLK frequency must

remain at 32 MHz (or 64 MHz if the divide by 2 prescalars are enabled).

NOTE: Nearly all timings in this datasheet assume that both I_OCLK and MEMCLK are running at 32 MHz (or

64 MHz with the divide by 2 prescalars on).

Increasing the memory clock frequency allows the system designer to take advantage of faster DRAM

memory. The CL-PS7500FE includes full synchronization at the interface between the memory and I/O

sub-systems to ensure safe operation under asynchronous conditions.

21.2 Power Management

The CL-PS7500FE includes power management circuitry that greatly enhances its suitability for battery

powered portable applications where power consumption is of paramount importance. There are three

power management modes:

192

CLOCKS, POWER SAVING, AND RESET

ADVANCE DATA BOOK v2.0

June 1997

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